3D Tunnel FETs With Increased Width For Drive Strength
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Solution Overview
Problem
Conventional thin-film transistors face challenges in scaling down to smaller dimensions due to limitations in subthreshold swing and variability in fabrication processes, making it difficult to extend their performance into the 10 nm or sub-10 nm range, necessitating new methodologies or technologies for future technology nodes.
Innovation Solution
The development of three-dimensional tunnel field effect transistors with increased gate width, utilizing non-planar architectures and materials like polycrystalline silicon, III-V materials, or semiconducting oxides, which enhance drive strength and performance while maintaining low voltage operation, effectively increasing transistor width and drive strength over conventional planar transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistor scaling is pursued, then device density increases, but subthreshold swing performance deteriorates and fabrication variability increases
Solution Approach 1:
The patent transitions from two-dimensional planar transistor architecture to three-dimensional vertical architecture. The channel is formed as a vertical structure extending from the substrate surface upward, with the gate wrapping around the channel in a multi-gate configuration. This dimensional change enables continued scaling of device density while maintaining effective gate control and subthreshold swing performance through the vertical channel structure.
Solution Approach 2:
The patent segments the gate structure into multiple gates that wrap around the vertical channel from different directions (front gate, back gate, and sidewall gates). This segmentation allows independent control of different channel regions and maintains effective electrostatic control over the entire channel, preventing performance deterioration as devices scale to smaller dimensions.
2Productivity
If multi-gate transistor dimensions are reduced, then device density increases, but fabrication process constraints become overwhelming
Solution Approach 1:
The patent employs a unified vertical channel structure that serves multiple functions: it provides the current conduction path, enables multi-gate control, and maintains compatibility with existing planar process flows. The vertical channel can be formed using standard semiconductor materials and processes, allowing the same fabrication infrastructure to produce both planar and vertical devices with minimal process modification.
3Power
If transistor width is increased to improve drive strength, then drive current increases, but device area increases reducing density
Solution Approach 1:
The patent moves the transistor's effective area from the horizontal plane to the vertical dimension. By creating a vertical channel that extends upward from the substrate, the device achieves increased effective channel width and drive strength through the vertical extent of the channel rather than through horizontal expansion. This allows high drive strength to be achieved while maintaining a compact horizontal footprint for high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-performance thin film tunnel field effect transistors with increased effective widths for scaled projected areas, improving drive strength and performance, particularly suitable for back-end logic, memory, and analog applications, and enabling monolithic integration of logic and memory in advanced SoCs.
Implementation Method 1
A gate electrode is over a channel portion of the channel material layer on the insulator structure
Implementation Method 2
thin film tunnel field effect transistors having relatively increased width
Data Source
AI summary
Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.