Three-Dimensional Turbo Code ECC for Flash Memory
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Solution Overview
Problem
Conventional approaches to error management in MLC flash memories are inefficient in achieving low uncorrectable error rates, especially in enterprise storage environments, due to high write amplification and degradation of signal-to-noise ratio over time, leading to reduced reliability and lifespan of flash memory devices.
Innovation Solution
A three-dimensional turbo code system is implemented, comprising primary, secondary, and tertiary error correction codes that are partially orthogonal to each other, along with a journaling filing system to reduce write amplification and extend flash memory cell life, ensuring efficient error correction and data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-layer BCH ECC is used in MLC flash memory, then the device complexity is low and ease of manufacture is good, but the uncorrectable error rate is high and reliability is insufficient for enterprise storage
Solution Approach 1:
The patent divides the error correction task into three independent layers: primary BCH ECC at the page level, secondary BCH ECC at the block level, and tertiary LDPC ECC at the device level. Each layer handles different error patterns and provides progressive error correction, transforming a single complex ECC system into multiple manageable layers that collectively achieve enterprise-grade reliability
Solution Approach 2:
The patent introduces a three-dimensional ECC architecture that operates at multiple hierarchical levels (page, block, device) rather than a single dimension. This multi-layered approach adds depth to the error correction capability, allowing the system to handle errors that would be uncorrectable by conventional single-layer ECC while maintaining reasonable implementation complexity through modular design
2Reliability
If strong ECC codes are applied to all flash memory regions, then the uncorrectable error rate decreases and reliability improves, but the write amplification increases and storage efficiency deteriorates
Solution Approach 1:
The patent applies different ECC strengths to different regions and data types within the flash memory device. Critical data regions receive stronger error correction protection, while less critical regions use lighter ECC schemes. This localized approach ensures high reliability for important data while minimizing write amplification and maximizing storage efficiency across the entire device
Solution Approach 2:
The patent implements error correction progressively through three layers, applying only the necessary level of correction for each error type encountered. The system performs partial error correction at each layer, moving to the next layer only when needed, thereby avoiding the excessive write amplification that would result from applying maximum-strength ECC to all data uniformly
3Quantity of substance
If MLC flash memory is used instead of SLC, then the storage capacity increases and cost decreases, but the program/erase cycle lifetime is reduced and signal-to-noise ratio degrades
Solution Approach 1:
The patent implements a multi-layer ECC system that proactively compensates for the inherent weaknesses of MLC flash memory before errors become uncorrectable. By establishing strong error correction capabilities in advance through three hierarchical layers, the system cushions against the reduced program/erase cycle lifetime and signal-to-noise ratio degradation, enabling MLC to achieve reliability levels previously only possible with more expensive SLC memory
Data Source
AI summary
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.