3D Turbo Code ECC for Flash Memory Reliability
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Solution Overview
Problem
Conventional approaches to error management in MLC flash memories are inefficient in achieving low uncorrectable error rates, especially in enterprise storage environments, due to high write amplification and degradation of signal-to-noise ratio over time, leading to reduced reliability and lifespan of flash memory devices.
Innovation Solution
A three-dimensional turbo code system is implemented, comprising primary, secondary, and tertiary error correction codes that are partially orthogonal to each other, along with a journaling filing system to reduce write amplification and extend flash memory cell life, ensuring efficient error correction and data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BCH error correction coding is used in MLC flash memory, then the device can store data over a specified number of program/erase cycles, but the uncorrectable error rate increases over time and becomes unacceptable for enterprise storage applications
Solution Approach 1:
The patent transitions from conventional one-dimensional BCH error correction coding to a three-dimensional turbo code system. This dimensional expansion allows the system to protect data across multiple layers (pages, page stripes, and page grids) simultaneously, achieving enterprise-grade reliability (1E-16 uncorrectable error rate) while maintaining compatibility with MLC flash memory's program/erase cycle characteristics.
Solution Approach 2:
The patent segments the flash memory into a hierarchical structure of pages, page stripes, and page grids, with dedicated error correction codes at each level. This segmentation allows the system to tackle errors at different scales and locations, improving overall reliability without requiring excessive redundancy at any single level, thus preserving program/erase cycle lifetime.
2Reliability
If stronger error correction coding is applied to achieve low uncorrectable error rates, then reliability improves, but write amplification increases and performance degrades
Solution Approach 1:
The patent implements a tiered error correction approach where the three-dimensional turbo code system applies different levels of correction strength at different hierarchical levels. Not all data requires the maximum correction strength, allowing the system to achieve enterprise-grade reliability while minimizing the total redundancy overhead and associated write amplification compared to applying uniform maximum-strength correction across all data.
3Quantity of substance
If MLC flash memory is used to reduce cost, then storage density improves and price decreases, but signal-to-noise ratio degrades and error rates increase
Solution Approach 1:
The patent compensates for MLC's inherently lower signal-to-noise ratio by introducing a three-dimensional error correction architecture. This dimensional expansion provides multiple layers of error protection, enabling the system to achieve enterprise-grade reliability (1E-16 uncorrectable error rate) despite the degraded signal quality inherent in high-density MLC flash memory.
Solution Approach 2:
The patent creates a composite error correction system combining three different coding schemes (primary BCH codes at the page level, secondary codes at the page stripe level, and tertiary Reed-Solomon codes at the page grid level). This composite approach leverages the strengths of different coding methods to achieve superior error correction capability that compensates for MLC's signal-to-noise ratio limitations.
4Ease of manufacture
If conventional ECC schemes are used, then implementation is simple, but achieving enterprise-grade error rates requires excessive redundancy and reduced storage efficiency
Solution Approach 1:
The patent implements a tiered error correction approach where the three-dimensional turbo code system applies different levels of correction strength at different hierarchical levels. Not all data requires the maximum correction strength, allowing the system to achieve enterprise-grade reliability while minimizing the total redundancy overhead and associated write amplification compared to applying uniform maximum-strength correction across all data.
Data Source
AI summary
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. A page is associated with a set of primary ECC codewords, and a page stripe is associated with a set of secondary codewords and primary over secondary parity (PoSP) ECC codewords. Two or more page stripes can form a page grid, wherein the page grid is associated with a group of tertiary ECC codewords, wherein the last page stripe of the page grid has a reduced payload capacity.