Three-Dimensional Turbo Code for Flash Drive Error Correction
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Solution Overview
Problem
Conventional approaches to error management in MLC flash memories are inefficient in achieving low uncorrectable error rates, especially in enterprise storage environments, due to high write amplification and degradation of signal-to-noise ratio over time, leading to reduced reliability and lifespan of flash memory devices.
Innovation Solution
A three-dimensional turbo code system is implemented, comprising primary, secondary, and tertiary error correction codes that are partially orthogonal to each other, along with a journaling filing system to reduce write amplification and extend flash memory cell life, ensuring efficient error correction and data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BCH error correction coding is used in MLC flash memory, then the implementation is simple and cost-effective, but the uncorrectable error rate is high and reliability is insufficient for enterprise storage
Solution Approach 1:
The patent segments the error correction task into three distinct coding layers: systematic BCH code for primary error correction, non-systematic BCH code for secondary correction, and Reed-Solomon code for tertiary correction. Each layer handles specific error patterns, collectively achieving enterprise-grade reliability (1E-16 uncorrectable error rate) while maintaining manageable complexity through modular design
Solution Approach 2:
The patent introduces a multi-dimensional error correction approach by combining three different ECC codes (systematic BCH, non-systematic BCH, and Reed-Solomon) operating in different dimensions and with different properties. This multi-layered coding scheme transforms the single-dimension conventional BCH approach into a multi-dimensional system, achieving superior error correction capability
2Reliability
If strong error correction coding is applied to achieve low uncorrectable error rates, then reliability improves, but write amplification increases and flash memory lifespan decreases
Solution Approach 1:
The patent implements dynamic gear selection that adapts the ECC strength based on real-time signal-to-noise ratio measurements. The controller monitors error rates and automatically switches between different ECC gears (code strengths), using stronger correction only when necessary. This dynamic adaptation achieves required reliability while minimizing write amplification and extending flash memory lifespan
3Reliability
If adaptive ECC gear selection is implemented, then reliability and efficiency are optimized, but the complexity of error management increases
Solution Approach 1:
The patent implements self-service through automatic gear selection where the flash controller autonomously monitors error rates, evaluates signal-to-noise ratio, and selects appropriate ECC gears without external intervention. The system self-adjusts coding strength based on real-time conditions, reducing the need for complex external error management while optimizing reliability and efficiency
4Quantity of substance
If MLC flash memory is used instead of SLC, then storage cost decreases and storage density increases, but program/erase cycle lifetime and signal-to-noise ratio deteriorate
Solution Approach 1:
The patent changes the parameter of ECC coding strength dynamically based on the degraded signal-to-noise ratio characteristics of MLC flash. By adapting the coding rate and code selection (BCH vs. Reed-Solomon) to the actual MLC error characteristics, the system achieves reliable operation despite the inherently lower signal quality of multi-level cells compared to single-level cells
Data Source
AI summary
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.