3D Two-Port Bit Cell for Dual-Port SRAM Area Efficiency
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Solution Overview
Problem
Conventional dual-port SRAM structures face challenges with larger area occupation, signal routing complexities, and read disturb issues due to their wider word line direction and increased periphery logic circuitry, which impact the aspect ratio and efficiency of semiconductor memory designs.
Innovation Solution
The implementation of three-dimensional semiconductor memory circuits with a read port array and bit cell array stacked vertically, utilizing tri-state buffer or transmission gate configurations for read port cells and pass transistors for bit cells, which eliminates the need for a keeper cell and reduces parasitic RC loading, enabling dual-port functionality without the drawbacks of conventional dual-port SRAMs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional dual-port SRAM structures use word lines in different metal layers, then dual-port functionality is achieved, but different capacitive loading occurs due to different metal layers
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture, placing read and write port arrays in different vertical layers. This dimensional change allows both ports to access the same bit cell array without requiring separate metal layers for word lines, thereby achieving dual-port functionality while maintaining uniform capacitive loading characteristics.
2Adaptability or versatility
If conventional dual-port SRAM structures are designed with wider word line direction, then dual-port access is enabled, but the aspect ratio of SRAM macro is impacted
Solution Approach 1:
By stacking the read port array and write port array vertically in different layers, the patent enables dual-port access without increasing the horizontal dimensions. This maintains a favorable aspect ratio for the SRAM macro, particularly benefiting wide I/O designs where the word line direction width would otherwise significantly impact the overall shape.
3Productivity
If conventional dual-port SRAM structures are implemented, then multiple reads or writes can occur simultaneously, but the periphery logic circuitry is doubled compared to single-port SRAM
Solution Approach 1:
The patent merges the functionality of separate read and write decoders and I/O circuits into shared structures. The read decoder and write decoder can be implemented using the same circuitry, and the I/O circuits serve both ports, thereby enabling simultaneous read/write operations while avoiding the doubling of periphery logic circuitry that would otherwise be required.
4Adaptability or versatility
If conventional dual-port SRAM structures are used, then dual-port functionality is achieved, but signal routing complexities increase
Solution Approach 1:
By utilizing vertical stacking with through-silicon vias (TSVs) and inter-layer vias, the patent simplifies signal routing for dual-port functionality. The bit cell array in the second layer can be directly connected to both read and write port arrays in the first layer through vertical vias, eliminating the need for complex horizontal routing that would otherwise be required to connect separate read and write ports in the same layer.
Data Source
AI summary
A semiconductor memory includes a read port array disposed on a first layer of a three-dimensional integrated circuit and a bit cell array disposed on a second layer of the three-dimensional integrated circuit. The second layer being vertically positioned above or below the first layer. At least one bit cell of the bit cell array is coupled to at least one read port cell of the read port array by a via extending from the first layer to the second layer.