3D UCIe Chiplet Interconnect Without Adapters or ESD Circuits
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Solution Overview
Problem
Current Universal Chiplet Interconnect Express (UCIe) implementations face scalability issues, limiting power-efficiency, area, latency, and reliability, particularly at smaller bump-pitches, and require die-to-die adapters and electrostatic discharge circuits.
Innovation Solution
The proposed Universal Chiplet Interconnect Express-Three Dimensional (UCIe-3D) interconnect provides a next-generation die-to-die solution that scales from 25 micrometer to sub-1 micron bump-pitch, eliminating the need for die-to-die adapters and electrostatic discharge circuits, with hardened physical layers and Network-on-chip Controllers directly interfacing to manage power and latency, enabling lower power consumption and higher bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current UCIe implementations are used, then basic interconnect functionality is provided, but scalability and power-efficiency are limited
Solution Approach 1:
The patent transitions from 2D planar interconnect architecture to 3D vertical stacking architecture. Multiple chiplets are stacked vertically with interconnects extending through the stack, enabling simultaneous data transmission across multiple layers. This dimensional change increases bandwidth capacity without proportionally increasing power consumption, as the vertical arrangement reduces signal path length and improves routing efficiency.
Solution Approach 2:
The interconnect is divided into multiple independent lanes that can operate simultaneously. Each lane handles separate data streams between chiplets, allowing parallel communication. This segmentation increases overall bandwidth while each individual lane maintains efficient power consumption, avoiding the need to scale up a single high-power connection.
2Reliability
If die-to-die adapters and electrostatic discharge circuits are included, then reliability is improved, but device complexity increases
Solution Approach 1:
The interconnect architecture uses standardized physical layer interfaces and protocols that can be uniformly applied across all chiplet connections. The same interconnect structure serves multiple functions: data transmission, error detection, and defect tolerance through redundant paths. This universality reduces design complexity compared to implementing separate specialized circuits for each function.
Solution Approach 2:
The patent implements built-in error correction codes and redundancy mechanisms directly into the interconnect structure. Defect tolerance is achieved through pre-configured backup paths and error detection/correction capabilities that are integrated into the basic interconnect design, rather than adding complex external protection circuits.
3Area of stationary object
If bump-pitch is reduced to increase density, then area efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs advanced signaling techniques and adjusted electrical parameters to compensate for variations introduced by smaller bump-pitches. The physical layer protocol includes training sequences and equalization mechanisms that adapt to the specific electrical characteristics of reduced-pitch interconnects, enabling reliable operation at sub-1 micron bump-pitches without requiring proportionally tighter manufacturing tolerances.
4Reliability
If hardened physical layers are used, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent integrates error detection and correction functionality directly into the physical layer data paths. Hardened logical effort is implemented by merging reliability functions with the core data transmission logic, so that error protection operates transparently without requiring separate complex control circuits. This integration achieves low bit error rates while maintaining relatively simple overall architecture.
Data Source
AI summary
Methods and apparatus relating to a Universal Chiplet Interconnect Express™ (UCIe™)-Three Dimensional (UCIe-3D™) interconnect which may be utilized as an on-package interconnect are described. In one embodiment, an interconnect communicatively couples a first physical layer module of a first chiplet on a semiconductor package to a second physical layer module of a second chiplet on the semiconductor package. A first Network-on-chip Controller (NoC) logic circuitry controls the first physical layer module. A second NoC logic circuitry controls the second physical layer module. Other embodiments are also claimed and disclosed.