3D Unipolar Logic Circuit with Vertical Stacking
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Solution Overview
Problem
Conventional CMOS logic integrated circuits face challenges in achieving low standby power and high density due to the limitations of feature size reduction, leading to increased costs and the need for innovative approaches beyond traditional lithography methods, particularly in utilizing new transistor materials like thin film amorphous metal oxides and compound semiconductors.
Innovation Solution
The development of novel unipolar circuits with vertical structures that employ capacitors for precharge and bootstrap operations, and clocked gate designs with ultra-short transistor channel lengths, fabricated using a deposition process instead of lithography, enabling low power consumption and high density integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional CMOS logic integrated circuits use both PMOS and NMOS transistors for high performance and low power, then performance and power efficiency are improved, but manufacturing cost increases and device complexity increases
Solution Approach 1:
The patent extracts one transistor type (PMOS) from the conventional CMOS pair, leaving only NMOS transistors in the circuit. This unipolar approach simplifies manufacturing by using a single transistor type while maintaining logic functionality through careful circuit design that compensates for the absence of complementary transistors.
Solution Approach 2:
The patent changes the electrical parameters of the unipolar circuit by introducing capacitors for precharge and bootstrap operations, and by using clocked gate designs. These parameter changes enable the single-transistor-type circuit to achieve power efficiency comparable to or better than conventional CMOS while reducing manufacturing complexity.
2Productivity
If feature size is reduced to increase transistor density, then productivity and integration density are improved, but manufacturing cost increases due to advanced lithography requirements
Solution Approach 1:
The patent transitions from planar 2D circuit layout to vertical 3D stacked structures. By stacking multiple logic gates and transistor layers vertically, the circuit achieves higher integration density without requiring proportional reduction in lateral feature size, thereby avoiding the exponential cost increase associated with advanced lithography nodes.
Solution Approach 2:
The patent implements nested structures where multiple logic gates are stacked vertically, with each gate containing transistors and interconnects arranged in three-dimensional configurations. This nesting approach maximizes the use of vertical space to increase effective transistor density while maintaining compatibility with existing lithography capabilities.
3Ease of manufacture
If unipolar logic is used to reduce manufacturing cost, then ease of manufacture is improved, but standby power consumption increases
Solution Approach 1:
The patent applies precharge operations using capacitors to prepare the circuit state before logic evaluation. By precharging nodes to appropriate voltage levels, the circuit eliminates the need for continuous current flow during standby periods, thereby reducing static power consumption while maintaining the simplicity of unipolar transistor implementation.
Solution Approach 2:
The patent implements clocked gate designs where logic operations are performed in periodic cycles synchronized with clock signals. During non-active periods, transistors are turned off and capacitors maintain stored charges, creating periodic operation patterns that minimize standby power consumption while preserving the manufacturing advantages of unipolar logic.
4Speed
If vertical structures with ultra-short transistor channel lengths are fabricated using deposition process, then speed and density are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces traditional lithography-based patterning with deposition-based fabrication for creating ultra-short transistor channels. By using atomic layer deposition or chemical vapor deposition to form conformal thin films that define channel lengths, the process achieves superior precision and uniformity compared to mechanical lithographic patterning, enabling sub-10nm channel lengths with controlled variability.
Data Source
AI summary
Apparatus and associated methods related to a three-dimensional integrated logic circuit that includes a columnar active region. Within the columnar active region resides an interdigitated plurality of semiconductor columns and conductive columns. A plurality of transistors is vertically arranged along each semiconductor column, which extends from a bottom surface of the columnar logic region to a top surface of the columnar logic region. The plurality of transistors are electrically interconnected so as to perform a logic function and to generate a logic output signal at a logic output port in response to a logic input signal received at a logic input port. Each of the plurality of conductive columns is adjacent to at least one of the plurality of semiconductor columns and extends along a columnar axis to one or more interconnection layers at the top and/or bottom surfaces of the columnar active layer.