3D Variable Resistance Memory With Junction FET
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Solution Overview
Problem
Current memory devices face limitations in integration density and switching performance, particularly in next-generation memory devices requiring high capacity, speed, and low power consumption, such as resistive memory devices like PCRAMs, ReRAMs, and MRAMs.
Innovation Solution
A 3D variable resistance memory device is developed, incorporating a semiconductor substrate with a string selection switch, channel layer, stacked gates, and a variable resistance layer, utilizing junction transistors to enhance integration density and switching performance through a driving method that selectively controls current paths in memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are integrated in a narrow area to improve integration density, then integration density is improved, but switching performance deteriorates
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to vertical 3D stacking architecture. Memory cells are stacked in multiple layers along the vertical dimension, allowing high integration density without compromising the switching performance of individual cells. Each stacked cell maintains proper transistor control and variable resistance layer characteristics despite the compact vertical arrangement.
Solution Approach 2:
The memory device is segmented into multiple functional layers including string selection switches, channel layers, gates, and variable resistance layers. This segmentation allows each component to be optimized independently for its specific function while collectively achieving high integration density and maintaining switching performance through proper layer-by-layer stacking.
2Reliability
If junction transistors are used to selectively control current paths, then switching performance is improved, but device complexity increases
Solution Approach 1:
The junction transistor structure serves multiple functions: it acts as a string selection switch to control current paths to specific memory cells, and simultaneously functions as part of the memory cell switching mechanism itself. This multi-functionality reduces the need for separate control components, thereby managing device complexity while maintaining excellent switching performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves integration density and ensures effective switching performance in memory devices, enabling efficient data read and write operations while maintaining a compact design, thus addressing the limitations of existing memory technologies.
Implementation Method 1
each of the memory cells includes a variable resistance layer, and a junction transistor configured to selectively provide current to the variable resistance layer
Data Source
AI summary
A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer.