3D Variable Resistance Memory Device Stacking Integration
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Solution Overview
Problem
Current resistive memory devices face challenges in achieving high integration density and stable stacking of memory cells with smaller critical dimensions, which limits their performance and efficiency.
Innovation Solution
The proposed variable resistance memory device includes a semiconductor substrate with a common source region, channel layer, cell gate electrodes, gate insulating layer, cell drain region, variable resistance layer, and bit line, manufactured through a method involving alternating interlayer insulating layers and selective etching to form stacked memory cells, allowing for improved integration density and switching characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are stacked in a 3D structure to improve integration density, then the number of memory cells per unit area increases, but the critical dimension becomes smaller and stacking stability deteriorates
Solution Approach 1:
The patent implements a stacked memory cell structure where multiple memory cells are vertically nested on top of each other. Each memory cell layer includes a channel layer, variable resistance layer, and electrode structures that are sequentially stacked, achieving high integration density while maintaining structural integrity through the nested configuration
Solution Approach 2:
The patent transitions from a planar 2D memory cell layout to a vertical 3D stacked structure. By extending the memory cell architecture in the vertical dimension (stacking multiple cell layers), the integration density is significantly improved without requiring proportionally smaller critical dimensions in the lateral plane
2Productivity
If the critical dimension is reduced to increase integration density, then more memory cells can be integrated, but the manufacturing precision and device stability worsen
Solution Approach 1:
The patent moves the integration scaling challenge from the lateral dimension to the vertical dimension. By stacking memory cells vertically, high integration density is achieved without requiring excessive reduction of critical dimensions, thereby maintaining device stability and manufacturing feasibility
Solution Approach 2:
The memory device is segmented into multiple discrete memory cell layers stacked vertically. Each layer contains complete functional elements (channel, variable resistance layer, electrodes), allowing independent formation and optimization of each cell while contributing to overall high density through vertical stacking
Data Source
AI summary
A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction. A gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes. A channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer.