3D Vertical FeRAM Memory String Array for High-Density Storage
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Solution Overview
Problem
Current 3D non-volatile memory circuits face challenges in achieving high-speed, low-power, and low-cost solutions suitable for high-density storage class memory applications, with existing technologies like 3D XPoint memory circuits experiencing high manufacturing costs and power dissipation due to sneak paths, and ferroelectric memory circuits lacking high-density capabilities.
Innovation Solution
A 3-dimensional vertical memory string array is developed using high-speed ferroelectric field-effect transistor (FET) cells with a zirconium-doped or silicon-doped HfO2 ferroelectric layer, a gate oxide layer, and conductive semiconductor regions, organized in a staircase configuration with global word line conductors, to provide low-cost, low-power, and high-density random-access memory capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ferroelectric materials (PZT, SBT) are used in FeFET, then dipole alignment for memory function is achieved, but ferroelectric layer thickness must be at least 70 nm which prevents high-density memory circuits
Solution Approach 1:
The patent changes the material parameter from conventional ferroelectric materials (PZT, SBT) to hafnium oxide (HfO2) and its doped variants. This material substitution enables the ferroelectric layer thickness to be reduced from the conventional minimum of 70 nm to much thinner dimensions while maintaining ferroelectric functionality, thereby enabling high-density memory circuits.
2Ease of operation
If 3D XPoint memory circuits are used, then bit-by-bit access suitable for SCM applications is achieved, but cross-point patterning requires double exposures which increases manufacturing cost
Solution Approach 1:
The patent segments the memory structure into vertically stacked components including multiple ferroelectric layer stacks arranged in a 3D configuration. This segmentation approach enables bit-by-bit access capability while using conventional single-exposure patterning processes, avoiding the need for complex cross-point double exposure manufacturing.
Solution Approach 2:
The patent transitions from planar 2D memory architecture to a 3D vertical stacked architecture. By stacking multiple ferroelectric layer structures vertically and providing electrical access through word lines and bit lines in different dimensions, the patent achieves high-density storage with simplified manufacturing processes.
3Ease of operation
If 3D XPoint memory circuits are used, then random-access capability is achieved, but phase-change material results in high leakage currents from sneak paths which increases power dissipation
Solution Approach 1:
The patent introduces selector devices as intermediary components between the memory cells and the read/write circuitry. These selector devices act as mediators that control and limit leakage currents from sneak paths, thereby reducing power dissipation while maintaining random-access capability. The selector devices enable precise control of current flow to selected memory cells only.
4Volume of moving object
If vertical NOR-type memory string arrays are used, then 3D vertical configuration is achieved, but complicated X and Y patterning schemes are required and power consumption is high
Solution Approach 1:
The patent implements a 3D vertical stacked architecture where multiple ferroelectric layer stacks are arranged vertically and accessed through word lines and bit lines extending in different dimensions. This vertical stacking approach achieves high memory density while using simplified conventional patterning processes, avoiding complicated X and Y patterning schemes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient programming and erasure operations in nanoseconds, reducing power consumption and manufacturing costs while achieving high-density storage, making it suitable for high-speed SCM applications.
Implementation Method 1
conventional ferroelectric materials, such as those based on lead zirconate titanate (PZT) and strontium bismuth tantalate (SBT), for example, do not provide high-density memory circuits. This is because the ferroelectric layer in an FeFET based on these materials must at least 70 nm thick.
Implementation Method 2
U.S. Pat. No. 6,067,244 to T. Ma, entitled 'Erroelectric Dynamic Random Access Memory,' filed on Sep. 16, 1998, discloses a ferroelectric field-effect transistor (FeFET) that can serve as a memory circuit, as dipole moments in the FeFET can be aligned in either one of two configurations by an electric field.
Data Source
AI summary
A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.