3D Vertical Inductors for IC Chip Area Reduction
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Solution Overview
Problem
Integrated circuits with inductors face challenges due to the large size of two-dimensional inductors, which occupy significant chip area and generate magnetic fields that interfere with linear circuitry, requiring substantial off-chip passive devices and increasing the size of the overall circuit package.
Innovation Solution
A method for forming inductors with a coil-like structure using vertical and horizontal members interconnected through copper layers, allowing for a compact, three-dimensional inductor design that extends through the substrate, enabling wafer-to-wafer bonding and reducing chip area usage while maintaining electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two-dimensional spiral inductors are used in integrated circuits, then inductors can be integrated on chip, but they occupy significant chip area and generate magnetic fields that interfere with linear circuitry
Solution Approach 1:
The patent transitions from two-dimensional planar spiral inductors to three-dimensional vertical inductors. The inductor structure extends through multiple layers (first layer, second layer, third layer) with vertical connections via vias, transforming the inductor geometry from a flat spiral to a stacked three-dimensional configuration. This dimensional change reduces the planar footprint while maintaining inductance functionality.
2Adaptability or versatility
If two-dimensional spiral inductors are used in integrated circuits, then inductors can be integrated on chip, but magnetic fields generated interfere with linear circuitry
Solution Approach 1:
By moving from planar 2D spirals to 3D vertical structures, the magnetic field distribution is altered. The vertical stacking configuration changes the spatial orientation of current loops, which modifies the magnetic field geometry and reduces coupling with planar linear circuitry on the same chip layer.
3Reliability
If off-chip passive devices are used, then inductor functionality is provided, but the overall circuit package size increases substantially
Solution Approach 1:
The patent merges the inductor function directly into the integrated circuit chip by fabricating three-dimensional inductors using the same semiconductor fabrication processes as the active devices. This integration eliminates the need for separate off-chip inductor components and their associated mounting hardware, thereby reducing the overall package volume.
4Ease of operation
If more input and output pins are added for passive devices, then connections to passive devices are enabled, but the chip size increases
Solution Approach 1:
The three-dimensional inductors are fabricated using the existing integrated circuit fabrication layers and interconnect structures. The inductor terminals are formed as part of the standard IC metallization layers, allowing connections to be made through existing chip I/O pins without requiring additional dedicated pins for passive device connections.
Data Source
AI summary
Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.