3D Vertical Transistor Memory Architecture for Higher Density
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased complexity and cost as feature sizes approach a lower limit, limiting memory density.
Innovation Solution
Implementing a 3D memory architecture with vertical transistors and a bonding interface between semiconductor structures, allowing for a stacked arrangement of memory cells and peripheral circuits, which reduces transistor area and simplifies interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication complexity and cost increase as feature sizes approach a lower limit
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked architecture. Memory cells are arranged in multiple layers stacked vertically, with each layer containing memory cells formed on different substrates that are bonded together. This vertical stacking enables continued memory density improvement without requiring further reduction of lateral feature sizes, thereby avoiding the fabrication complexity and cost increases associated with scaling planar devices to smaller dimensions.
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but manufacturing cost increases
Solution Approach 1:
The patent divides the memory device into multiple separate substrates or wafers, each containing a layer of memory cells. These substrates are fabricated independently using standard planar processing techniques, then bonded together to form the final stacked structure. This segmentation allows each substrate to be manufactured using cost-effective, well-established processes rather than requiring expensive advanced lithography for the entire device, thereby reducing manufacturing cost while achieving high memory density through vertical integration.
3Quantity of substance
If 3D memory architecture is implemented with stacked semiconductor structures, then memory density and I/O throughput are improved, but device structure complexity increases
Solution Approach 1:
The patent implements 3D memory architecture by stacking multiple semiconductor structures vertically, with memory cells arranged in layers along the vertical dimension. Each layer contains memory cells formed on separate substrates that are bonded together, creating a three-dimensional arrangement. This vertical stacking increases memory density and I/O throughput by providing multiple parallel access paths while managing structural complexity through systematic layering and bonding interfaces.
4Quantity of substance
If vertical transistors with gate structures contacting all sides of semiconductor body are used, then transistor area is reduced and memory density is improved, but fabrication precision requirements increase
Solution Approach 1:
The patent employs vertical transistors where the gate structure contacts all sides of the semiconductor body, creating a three-dimensional gate-all-around configuration. This vertical arrangement reduces the lateral footprint of each transistor compared to planar devices, thereby increasing memory density. The fabrication precision challenges are managed by forming the gate structure through sequential deposition and etching processes that wrap around the semiconductor body, allowing precise control of gate dimensions and positioning in the vertical dimension where lithographic resolution requirements are less stringent.
Data Source
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with all sides of the semiconductor body. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.