3D Vertical Memory Array Layout for Density Without Extreme Scaling
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased fabrication complexity and cost as feature sizes approach a lower limit, limiting memory density.
Innovation Solution
Implementing a 3D memory architecture with vertical transistors and peripheral circuits formed on separate substrates, bonded together to reduce chip size and increase memory density, using multi-gate transistors to enhance channel control and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density increases, but fabrication complexity and cost increase
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked architecture. Multiple memory cell layers are vertically stacked and bonded together, utilizing the third dimension to increase memory density without further reducing lateral feature sizes, thereby avoiding the fabrication complexity and cost associated with extreme scaling
2Quantity of substance
If feature sizes of memory cells approach a lower limit, then memory density approaches upper limit, but planar process and fabrication techniques become challenging and costly
Solution Approach 1:
The patent divides the memory device into multiple separate memory cell layers that are fabricated independently and then bonded together. Each layer can be manufactured using standard planar processes at larger feature sizes, avoiding the need for costly and complex fabrication techniques required for extreme scaling to smaller feature sizes
3Quantity of substance
If 3D memory architecture is implemented, then memory density increases and chip size reduces, but fabrication process complexity increases
Solution Approach 1:
The fabrication process is segmented into independent stages: each memory cell layer is fabricated separately using standard planar processes, then bonded to other layers. This segmentation allows complex 3D structures to be built from simpler components, reducing the complexity of individual fabrication steps while achieving high density through stacking
Solution Approach 2:
Bonding interfaces and interconnect structures serve as intermediaries between separate memory cell layers. These intermediary elements enable vertical integration and electrical connection between layers, allowing complex 3D functionality to be achieved through modular assembly rather than monolithic fabrication
Data Source
AI summary
A memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is disposed at one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with the second side of the first peripheral circuit away from the memory array structure.