3D Vertical Memory Two-Region Doping for Density
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Solution Overview
Problem
Conventional three-dimensional vertical memory (3D-MV) technologies face challenges in achieving large storage capacity and low storage cost due to large memory hole diameters and low storage density, leading to high costs and inefficiencies.
Innovation Solution
The introduction of a two-region 3D-MV structure with a lightly-doped region surrounding the memory hole and a low-resistivity region outside it, reducing memory hole diameter and implementing a shared 3D-MV with shared lightly-doped regions among memory cells to minimize spacing and enhance access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional 3D-MV structure is used with uniformly doped horizontal address lines, then the structure is simple to manufacture, but the memory hole diameter is large and storage density is low
Solution Approach 1:
The horizontal address line is divided into two regions with different doping concentrations: a lightly-doped region adjacent to the memory hole and a heavily-doped region away from it. This local differentiation allows the memory hole diameter to be reduced while maintaining electrical performance, directly resolving the contradiction between manufacturing precision and device complexity.
Solution Approach 2:
The horizontal address line is segmented into functionally distinct regions: a first region (lightly-doped) that interfaces with the memory hole and a second region (heavily-doped) that provides low-resistance current flow. This segmentation enables independent optimization of each region's properties, achieving smaller memory holes without excessive manufacturing complexity.
2Quantity of substance
If memory hole diameter is reduced to increase storage density, then storage capacity increases, but reverse leakage current increases
Solution Approach 1:
The lightly-doped region is positioned specifically adjacent to the memory hole where reverse leakage current originates. This localized light doping reduces the electric field intensity at the memory hole interface, effectively suppressing reverse leakage current while allowing the memory hole diameter to be reduced for higher storage density.
Solution Approach 2:
The lightly-doped region acts as an intermediary layer between the memory hole and the heavily-doped region. It mediates the electrical field distribution, reducing peak field intensity at the memory hole interface to minimize reverse leakage, while still allowing efficient current flow through the connected heavily-doped region.
3Loss of time
If horizontal address line resistance is reduced to improve access time, then access speed increases, but the structure becomes more complex
Solution Approach 1:
The heavily-doped region is positioned in the horizontal address line away from the memory hole interface, specifically to reduce electrical resistance and improve current flow. This localized heavy doping reduces access time without requiring complex overall structure, as only specific regions are differentially doped rather than the entire line.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in smaller memory holes, denser memory arrays, and improved performance by reducing reverse leakage current and access time, while maintaining high storage capacity and low storage costs.
Implementation Method 1
both the P-N junction diode and the Schottky diode preferably comprise a lightly-doped region. For example, the P-N junction diode preferably has a P+/N−/N+ structure
Implementation Method 2
The diode 14 has two terminals: a positive terminal (also known as anode) 1+ and a negative terminal (also known as cathode) 1−. In general, a diode 14 favors current flow from its anode 1+ to its cathode 1−, but not the opposite.
Implementation Method 3
The resistance of the programmable layer 12 can be changed by at least an electrical programming signal
Data Source
AI summary
In a shared three-dimensional vertical memory (3D-MV), each horizontal address line comprises at least two regions: a lightly-doped region and a low-resistivity region. The lightly-doped region is formed around selected memory holes and shared by a plurality of low-leakage memory cells. The low-resistivity region forms a conductive network to reduce the resistance of the horizontal address line.