3D Vertical Memory Cell Layout for High-Density Scaling
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to increased complexity and cost as feature sizes decrease, limiting memory density, and existing transistors have horizontal structures that complicate interconnect arrangements and increase leakage current.
Innovation Solution
A memory device with vertically arranged transistors and a 3D memory architecture that includes a semiconductor body with a word line gate and a plate line gate, eliminating the need for capacitor storage and simplifying interconnect structures, allowing for reduced area occupation and improved fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to a three-dimensional architecture where the transistor channel extends vertically through a dielectric stack. This dimensional change allows memory density to increase without proportionally increasing fabrication complexity, as the vertical channel structure can be formed using standard deposition and etching processes applied to layered materials.
Solution Approach 2:
The memory device is segmented into distinct functional regions: a semiconductor layer, a stacked structure with alternating dielectric and conductive layers, and peripheral circuits. This segmentation allows each component to be optimized and fabricated independently, reducing overall fabrication complexity while maintaining high memory density.
2Reliability
If horizontal transistor structures are used, then interconnect arrangements become complicated and leakage current increases
Solution Approach 1:
The transistor channel is oriented vertically through the dielectric stack rather than horizontally in the plane. This vertical orientation reduces the footprint of the transistor, simplifies interconnect routing, and improves reliability by reducing leakage current paths that are present in planar structures.
Solution Approach 2:
The gate electrode and interconnect structures are merged with the stacked architecture, where conductive layers within the stack serve dual functions as both gate electrodes and interconnect pathways. This integration reduces the number of separate interconnect layers needed and simplifies the overall device structure.
Data Source
AI summary
A memory device includes a semiconductor layer; a peripheral circuit disposed on the semiconductor layer; and an array of memory cells disposed aside the peripheral circuit on the semiconductor layer. Each of the memory cells includes a semiconductor body extending in a first direction, a first end of the semiconductor body is in contact with the semiconductor layer; a word line gate extending in a second direction perpendicular to the first direction; a plate line gate extending in the second direction; and a dielectric layer disposed between the semiconductor body and the word line gate and the plate line gate.