3D Vertical Negative Differential Resistance Element for Multi-State Logic

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Solution Overview

Problem

Existing negative differential resistance elements with single peaks limit the miniaturization and integration of multi-notation circuits due to area constraints and increased power consumption when trying to generate multiple peaks, as they require additional devices or resistance components.

Innovation Solution

A 3-dimension vertical structure negative differential resistance element is created using semiconductor materials and insulators to form multiple resistance paths and peaks, reducing device area and enabling multiple state logic devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If additional devices or resistance components are added to generate multiple peaks, then multi-notation circuit states can be achieved, but device area increases and miniaturization is limited

Engineering Contradiction:

Improvemulti-notation circuit statesVSAvoiddevice area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent transitions from planar two-dimensional resistance structures to three-dimensional vertical resistance structures. By stacking multiple resistance elements vertically and utilizing vertical current paths, the invention achieves multiple resistance states without increasing lateral device area, thereby enabling multi-notation circuits while maintaining compact footprint

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested vertical stacking where multiple resistance elements are positioned at different vertical levels within a compact footprint. The first and second resistance elements are stacked vertically with insulating layers between them, creating a nested configuration that maximizes space utilization and enables multiple resistance states in a minimal area

Inventive Principle:

Principle #7Nested doll (Nesting)

2Adaptability or versatility

If additional devices or resistance components are added to generate multiple peaks, then multi-notation circuit states can be achieved, but power consumption increases

Engineering Contradiction:

Improvemulti-notation circuit statesVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The patent combines multiple resistance elements and current paths into a single integrated vertical structure. By merging the first resistance element, second resistance element, and insulating layers into one compact stacked configuration, the invention achieves multiple resistance states while minimizing the total number of discrete components and reducing overall power consumption

Inventive Principle:

Principle #5Merging (Combining)

3Ease of manufacture

If conventional two-dimensional resistance structures are used, then manufacturing is simpler, but device scaling and integration are limited

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoiddevice scaling and integration

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent employs vertical stacking of resistance elements along the z-axis, transforming the conventional two-dimensional planar layout into a three-dimensional structure. This dimensional transition enables continued device scaling and integration by utilizing the vertical dimension, thereby overcoming the limitations of planar scaling while maintaining compatibility with standard semiconductor manufacturing processes

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces device area, enhances integration, and allows for the creation of multi-state memory and logic elements with multiple peaks, improving scaling and power efficiency.

Implementation Method 1

a first semiconductor material that is deposited in some other region and the first electrode of the substrate

Methodology Applied

Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS11437572B2Negative differential resistance element having 3-dimension vertical structure

Publication Date: 2022.09.06 RES & BUSINESS FOUND SUNGKYUNKWAN UNIV

AI summary

Provided is a negative differential resistance element having a 3-dimension vertical structure. The negative differential resistance element having a 3-dimension vertical structure includes: a substrate; a first electrode that is formed on the substrate to receive a current; a second semiconductor material that is formed in some region of the substrate; a first semiconductor material that is deposited in some other region and the first electrode of the substrate and some region of an upper end of the second semiconductor material; an insulator that has a part vertically erected from the substrate, the other part vertically erected from the second semiconductor material, and an upper portion stacked with a first semiconductor material; and a second electrode that is formed at an upper end of the second semiconductor material to output a current, thereby significantly reducing an area of the device and greatly improving device scaling and integration.