3D Vertical OTP Memory With Antifuse Cells And Vertical Address Lines
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Solution Overview
Problem
Conventional three-dimensional one-time-programmable memory (3D-OTP) faces challenges with high storage cost, limited number of OTP levels due to complex lithography requirements, and difficulty in planarization as storage capacity increases, along with issues from leaky OTP cells.
Innovation Solution
The development of a three-dimensional vertical one-time-programmable memory (3D-OTPV) with vertically stacked OTP strings and horizontal address lines, using an antifuse layer and quasi-conductive diodes, and a full-read mode to address leakage current, allowing for reduced lithography steps and increased OTP levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the storage capacity of 3D-OTPH exceeds 100 Gb, then the minimum feature size goes to 1×nm requiring high-precision lithography, but this increases the 3D-OTP cost
Solution Approach 1:
The patent transitions from horizontal address lines in 3D-OTPH to vertical address lines in 3D-OTPV. This dimensional change allows the memory structure to achieve high storage capacity without requiring extremely small lateral feature sizes, thereby avoiding the need for complex high-precision lithography processes while maintaining cost-effectiveness
2Quantity of substance
If more OTP levels are vertically stacked in 3D-OTPH, then storage density increases, but planarization becomes more and more difficult
Solution Approach 1:
By changing from horizontal to vertical address lines, the patent enables easier planarization of stacked OTP levels. The vertical configuration allows for better control and flattening of multiple stacked layers without the compounding planarization difficulties encountered in horizontal configurations, thus enabling higher storage density through increased stacking levels
3Quantity of substance
If vertical OTP strings are stacked to increase storage capacity, then storage density improves, but the number of lithography steps increases
Solution Approach 1:
The vertical address line configuration enables the formation of multiple OTP levels with fewer lithography steps compared to horizontal configurations. This dimensional change simplifies the manufacturing process by reducing the number of patterning operations required, thereby improving production efficiency while achieving high storage capacity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a higher storage capacity with lower costs, improved planarization, and proper functionality even with leaky OTP cells by simplifying lithography and enhancing read operations.
Implementation Method 1
The antifuse comprises an antifuse layer, which is a layer of insulating dielectric (e.g. silicon oxide, or silicon nitride) and is irreversibly switched from a high-resistance state to a low-resistance state during programming
Implementation Method 2
The diode comprises a quasi-conductive layer, which is broadly interpreted as any layer whose resistance at the read voltage (i.e. the read resistance) is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage
Data Source
AI summary
The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTPV). It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. The horizontal address lines and the vertical address lines comprise oppositely-doped semiconductor materials.