3D Vertical Memory Array Access for Read/Write Parallelism
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Solution Overview
Problem
Conventional memory devices face limitations in read/write throughput due to parallelism issues, as simultaneous access to memory cells on different word line/bit line pairs affects unaddressed cells, and current-related limitations inhibit addressing multiple cells on the same line, leading to misfunctioning and voltage drops.
Innovation Solution
A 3D vertical memory array with word lines organized in planes separated by insulating material and bit lines perpendicular to these planes, allowing simultaneous access to multiple memory cells through independent selection and deselection of bit and word lines, using self-selecting chalcogenide materials and CMOS under Array technology for drivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory cell arrays are used with shared access lines, then device complexity is reduced, but parallel access capability deteriorates because unaddressed cells are also biased when addressing cells on different word line/bit line pairs
Solution Approach 1:
The patent divides the memory array into multiple independent sub-arrays, each with its own dedicated access lines. This segmentation allows simultaneous addressing of cells across different sub-arrays without mutual interference, as each sub-array operates independently with its own word lines and bit lines, thereby enabling true parallel access while maintaining manageable complexity within each sub-array.
Solution Approach 2:
The patent extends the memory array architecture from a two-dimensional planar structure to a three-dimensional configuration by stacking multiple sub-arrays vertically. This dimensional transition allows access lines to be routed through different layers and planes, providing spatial separation that enables simultaneous access to cells at different positions without signal interference, thus improving parallel access capability.
2Productivity
If multiple memory cells on the same access line are addressed simultaneously, then read/write throughput is improved, but voltage drops and misfunctioning occur due to current-related limitations and ohmic voltage drop on access lines
Solution Approach 1:
The patent segments the memory array into multiple sub-arrays with dedicated access lines, distributing the current load across separate physical paths. When multiple cells are accessed simultaneously, they are routed through different access lines within their respective sub-arrays, preventing cumulative voltage drops and current-induced misfunctioning that would occur if multiple cells shared the same access line.
Solution Approach 2:
The patent introduces selection transistors as intermediary elements between the access lines and memory cells. These transistors act as controlled switches that regulate current flow, allowing multiple cells to be accessed simultaneously while maintaining voltage stability. The transistors isolate the effects of individual cell currents, preventing the ohmic voltage drops from propagating and causing misfunctioning in other addressed cells.
Data Source
AI summary
The present disclosure provides a memory apparatus and a method for accessing a 3D vertical memory array. The 3D vertical memory array comprises word lines organized in planes separated from each other by insulating material, bit lines perpendicular to the word line planes, memory cells coupled between a respective word line and a respective bit line. The apparatus also comprises a controller configured to select multiple word lines, select multiple bit lines, and simultaneously access multiple memory cells, with each memory cell at a crossing of a selected word line and a selected bit line. The method comprises selecting a multiple word lines, selecting multiple bit lines and simultaneously accessing multiple memory cells, with each memory cell at a crossing of a selected word line of the selected multiple word lines and a selected bit line of the selected multiple bit lines. A method of manufacturing a 3D vertical memory array is also described.