3D Vertical Transistor Memory Cells for Higher Density
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to limitations in process technology, circuit design, programming algorithms, and fabrication processes, leading to density limitations and increased costs.
Innovation Solution
The development of semiconductor devices with vertical transistors, featuring a semiconductor layer with a low leakage value, a gate dielectric layer, and a gate electrode, along with capacitors coupled to the semiconductor layer, enhances memory density and reduces cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and fabrication processes, then memory density increases, but process complexity and manufacturing costs increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to vertical (3D) memory cell architecture. The vertical transistor structure with channel extending in the vertical direction and gate electrode wrapping around the channel from multiple sides enables memory cells to utilize the third dimension, achieving higher memory density without proportionally increasing process complexity.
Solution Approach 2:
The vertical transistor is segmented into distinct functional regions: vertical channel portion, lateral channel portions, first gate electrode for first lateral portions, and second gate electrode for second lateral portions. This segmentation allows independent optimization and control of different channel regions, simplifying the fabrication process while maintaining high density.
2Quantity of substance
If planar memory cells are scaled down further, then memory density approaches upper limit, but fabrication techniques become challenging and costly
Solution Approach 1:
By moving to vertical architecture, the patent achieves higher memory density without the diminishing returns that plague scaled planar devices. The vertical channel and wrapped gate structure enable continued scaling benefits while maintaining fabrication feasibility through standardized processes.
Solution Approach 2:
The vertical transistor structure serves multiple functions: the vertical channel provides high-density packing, the lateral channels enable contact access, and the wrapped gate electrodes provide control over different channel regions. This multi-functionality achieves high density without requiring multiple specialized fabrication steps.
3Area of moving object
If vertical transistors with wrapped gate electrodes are implemented, then memory area efficiency increases, but device structure complexity increases
Solution Approach 1:
The gate structure is segmented into first and second gate electrodes that wrap around different lateral portions of the channel. This segmentation simplifies the fabrication process by allowing each gate electrode to be formed and controlled independently, reducing the complexity of forming a completely continuous wrapped gate.
Solution Approach 2:
The patent utilizes vertical stacking to achieve high memory area efficiency. By arranging capacitors and transistors in vertical layers rather than spreading them out laterally, the design maximizes the use of vertical space, achieving high density without requiring overly complex lateral interconnect structures.
Data Source
AI summary
Three-dimensional (3D) semiconductor devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device comprises a plurality of vertical transistors, each comprising: a semiconductor layer having a leakage value lower than a pico-ampere and comprising a vertical semiconductor portion and at least one lateral semiconductor portion, a gate dielectric layer comprising a vertical gate dielectric portion on the vertical semiconductor portion and extending in the vertical direction, a gate electrode on the gate dielectric layer and separated from the semiconductor layer by the gate dielectric layer. The disclosed semiconductor device further comprises a plurality of capacitors each coupled with the semiconductor layer of a corresponding one of the plurality of vertical transistors.