3D Vertically-Integrated FETs for CMOS Cell Footprint Reduction
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Solution Overview
Problem
The challenge in reducing the footprint size of CMOS cell circuits in integrated circuits (ICs) is that the number of fins in FinFETs cannot be reduced beyond one fin, limiting the potential for further area reduction in standard cell layouts.
Innovation Solution
The implementation of three-dimensional (3D) vertically-integrated Field-Effect Transistors (FETs) for CMOS cell circuits, where a second semiconductor layer with a second FET is stacked above a first semiconductor layer, overlapping the channel structure of the first FET to reduce the footprint size, while maintaining unobstructed vertical access to metal layers through strategically located contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If FinFETs are used with multiple fins to increase current flow area, then the cross-sectional area of current flow increases, but the horizontal area occupied by the transistor increases
Solution Approach 1:
The patent transitions from two-dimensional lateral arrangement of multiple fins to three-dimensional vertical stacking of FET channels. Multiple channels are arranged vertically along the Z-axis rather than horizontally, allowing increased current flow capability without proportionally increasing the horizontal footprint. The channel structures extend in the vertical direction, enabling more channels to be packed within the same planar area.
Solution Approach 2:
The patent implements a nested configuration where channel structures are positioned within or alongside each other in the vertical dimension. The first channel structure and second channel structure are arranged such that they share overlapping horizontal projections, creating a space-efficient nested layout that maximizes current flow area while minimizing horizontal occupation.
2Area of stationary object
If the number of fins in FinFETs is reduced to one fin, then the horizontal area is reduced, but the cross-sectional area of current flow cannot be increased further
Solution Approach 1:
The patent compensates for reducing the number of lateral fins by introducing vertical stacking of channel structures. Instead of increasing current flow area through multiple horizontal fins, the invention stacks multiple channels vertically, maintaining a single-fin lateral footprint while achieving enhanced current flow capability through the third dimension.
Solution Approach 2:
The patent merges multiple channel structures into a single integrated vertical stack, combining their current flow capabilities while occupying a reduced horizontal footprint. The first channel structure and second channel structure are combined in the vertical dimension, creating a compact configuration that achieves high current flow with minimal footprint area.
3Area of stationary object
If FETs are vertically stacked to reduce footprint size, then the footprint area is reduced, but vertical access to metal layers for interconnections may be obstructed
Solution Approach 1:
The patent segments the vertical stack into distinct regions with dedicated access points. The first channel structure and second channel structure are positioned at different vertical levels with staggered configurations, creating separate access pathways to metal layers. This segmentation allows independent interconnection routing for each channel without mutual obstruction, reducing overall interconnection complexity despite the vertical integration.
Data Source
AI summary
A 3D vertically integrated FET for CMOS cell circuits is disclosed. Vertically integrating FETs for a 3D cell circuit reduces the footprint size of an IC chip. To reduce a CMOS cell circuit footprint, a PFET and an NFET are vertically integrated by stacking a second semiconductor layer including a second FET above a first semiconductor layer including a first FET, such that the channel structure of the second FET overlaps the channel structure of the first FET. The first FET may be an NFET, and the second FET may be a PFET, or vice versa. The longitudinal axis of the first FET channel structure may extend in a first plane parallel to a second plane including the longitudinal axis of the second FET channel structure. The longitudinal axes may be parallel or at an angle to each other, such that the second channel structure overlaps the first channel structure.