3D Semiconductor Via Allocation for Low-Delay Interlayer Routing
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Solution Overview
Problem
The challenge in manufacturing three-dimensional semiconductor devices is to efficiently connect through-via structures between stacked semiconductor layers while minimizing routing congestion and signal delay, as existing methods often result in unnecessary detour routing that degrades signal timing characteristics.
Innovation Solution
A method and computing system that identify candidate locations for through-via structures, calculate connection costs, and allocate these structures to optimize matching pairs with nets, using algorithms like the Hungarian Algorithm to determine the most suitable connections, thereby reducing routing wire length and congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If through-via structures are connected to nets using existing routing methods, then connectivity between semiconductor layers is achieved, but routing wire length increases and signal delay degrades due to unnecessary detours
Solution Approach 1:
The patent applies preliminary action by performing global routing optimization before final via allocation. The system pre-calculates optimal routing paths and identifies suitable via locations in advance, ensuring that subsequent via-to-net connections follow the most efficient paths without unnecessary detours, thereby minimizing signal delay while maintaining connectivity.
Solution Approach 2:
The patent utilizes another dimension by introducing a via allocation dimension that operates independently from traditional planar routing. By treating via locations as separable entities that can be optimally matched to nets based on spatial relationships and routing costs, the system transforms the two-dimensional routing problem into a multi-dimensional optimization problem that simultaneously considers via placement, net connection, and path efficiency.
2Ease of manufacture
If through-via structures are allocated without optimization, then manufacturing process is simpler, but routing congestion increases and connectivity efficiency decreases
Solution Approach 1:
The patent applies segmentation by dividing the via allocation process into distinct stages: candidate via location identification, net requirement analysis, cost calculation, and optimal pairing. This segmented approach breaks down the complex routing optimization into manageable steps that can be processed systematically, reducing routing congestion while maintaining manufacturing feasibility through structured decision-making.
Solution Approach 2:
The patent implements feedback by calculating routing costs based on the spatial relationships between via candidates and nets, then using this cost information to iteratively improve via allocation decisions. The system continuously refines the allocation by evaluating routing congestion and signal path efficiency, adjusting via-to-net assignments to minimize overall system complexity while preserving ease of manufacture.
Data Source
AI summary
A method and a computing system, for manufacturing a three-dimensional semiconductor device including first and second semiconductor device layers, are provided. The method includes: identifying candidate locations in a via area of the first semiconductor layer; identifying nets of the second semiconductor layer to be connected to through-via structures corresponding to the candidate locations; identifying a plurality of connection costs respectively corresponding to connections between the through-via structures and the nets; identifying pairs of the nets and the through-via structures, based on the plurality of connection costs; allocating the through-via structures according to the pairs; forming the through-via structures at the candidate locations; and forming electrical connections between the through-via structures.