3D Semiconductor Via Fill Structure to Prevent Seam Formation
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deteriorated operational properties, necessitating improvements in electrical characteristics and productivity while maintaining high integration density.
Innovation Solution
A three-dimensional semiconductor device design featuring a back-side metal layer, active regions with channel and source/drain patterns, an interlayer insulating layer, and a penetration conductive pattern with a seed and main layer, where the inhibitor covers the side surface of the seed layer, enhancing electrical connectivity and reducing seam formation during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to increase integration density, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically-stacked transistors. Multiple active regions are stacked vertically to increase integration density while maintaining adequate channel dimensions for reliable operation. The vertical stacking allows more devices to be packed in the same footprint without further scaling the critical dimensions of individual transistors.
2Device complexity
If conventional fabrication methods are used for three-dimensional devices, then manufacturing complexity increases, but productivity decreases
Solution Approach 1:
An inhibitor layer is deposited on the side surfaces of penetration holes before filling with conductive material. This preliminary action prevents seam formation during the filling process, eliminating the need for subsequent seam removal steps and reducing overall manufacturing complexity while improving productivity.
Solution Approach 2:
The inhibitor acts as an intermediary material between the penetration hole wall and the conductive fill material. It prevents direct contact that would cause seams, while still allowing complete filling of the penetration hole. This intermediary layer simplifies the fabrication process by preventing defects that would otherwise require additional correction steps.
3Loss of time
If penetration holes are filled without inhibitor, then processing time is reduced, but seam formation increases causing fabrication failures
Solution Approach 1:
The inhibitor is deposited in advance before the conductive fill material is deposited. This preliminary coating prevents seam formation during filling, ensuring fabrication success without requiring additional post-processing steps to remove seams, thus maintaining efficient processing time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves electrical characteristics and productivity by increasing integration density and reducing processing time, while minimizing failures in subsequent fabrication steps, thus addressing the challenges posed by scaled-down MOS-FETs.
Implementation Method 1
an inhibitor covering a side surface of a lower portion of the penetration conductive pattern. The inhibitor includes a carbon atom
Implementation Method 2
growing a main layer using the seed layer as a seed to fill the penetration hole
Data Source
AI summary
The present disclosure relates to three-dimensional semiconductor devices. An example three-dimensional semiconductor device includes a back-side metal layer, a lower active region on the back-side metal layer, the lower active region including a lower channel pattern and a lower source drain pattern connected with the lower channel pattern, an upper active region on the lower active region, the upper active region including an upper channel pattern and an upper source drain pattern connected with the upper channel pattern, an interlayer insulating layer enclosing the lower and upper source drain patterns, a penetration conductive pattern extending through the interlayer insulating layer in a vertical direction, and an inhibitor covering a side surface of a lower portion of the penetration conductive pattern. The inhibitor includes a carbon atom.