3D Via Structure Layout Without Etch Delay Layers
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Solution Overview
Problem
Existing 3D semiconductor packages face challenges in enhancing data speed and reducing power consumption, particularly in the vertical interconnects through silicon vias (TSVs), which affect the performance and reliability of semiconductor devices.
Innovation Solution
The semiconductor device incorporates via structures with varying diameters and undercut regions to optimize signal and power transfer paths, eliminating the need for an etch delay layer, thereby improving data processing speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If via structures with varying diameters and undercut regions are used, then data processing speed is improved and power consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies asymmetry by creating via structures with non-uniform diameters along their length and intentional undercut regions. The first via structure has a first diameter at its upper portion and a second diameter at its lower portion, while the second via structure has a third diameter greater than the first diameter. This asymmetric geometry optimizes electrical performance and signal integrity, directly improving data processing speed while managing power consumption.
Solution Approach 2:
The patent segments the via structures into distinct regions with different diameters and introduces undercut regions as separate geometric features. The via structures are divided into upper portions with larger diameters and lower portions with smaller diameters, with undercut regions creating horizontal protrusions. This segmentation allows optimization of different via sections for different functions, enhancing overall device performance.
2Reliability
If via structures with varying diameters and undercut regions are used, then reliability is improved by eliminating etch delay layers, but manufacturing precision requirements increase
Solution Approach 1:
The patent extracts and eliminates the etch delay layer from the via structure configuration. By removing this intermediate layer, the design achieves more direct electrical connections and simplifies the overall stack architecture. The undercut regions and varying diameters compensate for the removed layer's function, maintaining reliability while reducing manufacturing steps and precision requirements associated with etch delay layer formation.
Solution Approach 2:
The patent changes the geometric parameters of the via structures by varying diameters along their length and introducing undercut regions. These parameter changes optimize electrical characteristics such as resistance and capacitance, improving signal integrity and power efficiency. The parameter variations are designed to achieve target performance metrics while accommodating manufacturing tolerances.
Data Source
AI summary
A semiconductor device including a semiconductor substrate, an interlayer insulation layer on the semiconductor substrate, a first via structure passing through the semiconductor substrate and the interlayer insulation layer and having a first diameter, and a second via structure passing through the semiconductor substrate and the interlayer insulation layer, the second via structure having a second diameter greater than the first diameter, at a same vertical level may be provided. A sidewall of the first via structure may include at least one undercut region horizontally protruding toward a center of the first via structure, and an outer sidewall of the second via structure may be in contact with either the semiconductor substrate or the interlayer insulation layer at an area above the undercut region.