3D Wafer-Bonded Inductor Structure for Smaller IC Footprints
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Solution Overview
Problem
The integration of inductor components in semiconductor devices poses challenges due to the need for smaller footprints and reduced board space, particularly in circuits requiring voltage-controlled oscillators, low noise amplifiers, and power amplifiers, which are typically manufactured on a single semiconductor wafer.
Innovation Solution
A three-dimensional inductor structure is integrated vertically between two integrated circuit components, comprising a first and second metal level with dielectric regions and interconnect vias, allowing for independent control of inductance parameters through adjustable thicknesses and heights of dielectric levels and vias, facilitating wafer-level bonding and reduced footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If inductor components are integrated into semiconductor devices, then board space is reduced and integration efficiency is enhanced, but manufacturing complexity increases due to the need for precise control of inductance parameters through multiple dielectric levels and interconnect vias
Solution Approach 1:
The patent transitions from planar inductor layouts to a three-dimensional vertical structure. The inductor is formed with metal levels extending in the vertical direction between two bonded semiconductor wafers, utilizing the third dimension (height) to achieve compact footprint while maintaining controllable inductance through adjusted metal level heights and spacing.
Solution Approach 2:
The patent enables independent control of inductance parameters by adjusting the thicknesses and heights of dielectric levels and interconnect vias. This parameter optimization allows precise tuning of inductance values while maintaining a compact integrated structure, resolving the contradiction between compact size and manufacturing control.
2Area of moving object
If a three-dimensional inductor structure is used vertically between integrated circuit components, then footprint is reduced, but device complexity increases due to multiple metal levels, dielectric regions, and interconnect vias
Solution Approach 1:
The inductor structure is nested within the vertical space between two bonded semiconductor wafers. The first and second metal levels with their associated dielectric regions and interconnect vias are integrated into the existing wafer structure, utilizing the vertical volume that would otherwise be empty space, thereby achieving compact footprint without proportionally increasing structural complexity.
Solution Approach 2:
The patent employs vertical stacking of metal levels and dielectric regions to create a three-dimensional inductor. This vertical arrangement in the height dimension allows the inductor to occupy minimal planar footprint while the complexity is distributed along the vertical axis, effectively managing the footprint versus complexity trade-off.
3Productivity
If inductor structures are integrated into semiconductor devices, then integration efficiency is enhanced, but manufacturing precision requirements increase due to the need for controlled inductance values through precise dielectric and via dimensions
Solution Approach 1:
The inductor structure is fabricated as part of the standard semiconductor manufacturing process before wafer bonding. The metal levels and dielectric regions are formed using conventional photolithography and deposition techniques, with inductance parameters predetermined by design. This preliminary fabrication approach enables high integration efficiency while maintaining manufacturing precision through established process control methods.
Solution Approach 2:
The patent achieves precise inductance control by optimizing multiple geometric parameters including metal level thickness, dielectric layer thickness, and via dimensions. By adjusting these parameters within standard manufacturing tolerances, the design achieves desired inductance values without requiring excessive manufacturing precision, thus maintaining high integration efficiency.
Data Source
AI summary
The disclosed subject matter relates generally to an inductor structure integrated in a semiconductor device formed from bonded wafers, in which the semiconductor device has a three-dimensional inductor structure aligned vertically between two integrated circuit (IC) components. The inductor structure has a first metal level and a second metal level, the first metal level being in a different wafer from the second metal level.