3D Semiconductor Wafer Structure for High-Voltage Deep Junctions
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Solution Overview
Problem
Conventional semiconductor wafers, particularly single crystal epitaxial wafers, face limitations in thickness, cost, defect density, and compatibility with high-voltage large-power semiconductor chip production, restricting the development of high-performance power semiconductor devices with increasing voltage requirements.
Innovation Solution
A three-dimensional semiconductor wafer design featuring a semiconductor wafer unit with a connection layer and a conduction layer, arranged on the bottom surface, which forms a deep-junction structure for high voltage, simplifying production and reducing power loss, defect density, and thermal stress, while enabling higher working voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the epitaxial layer thickness is increased to meet high-voltage large-power semiconductor chip requirements, then the voltage handling capability is improved, but the cost and defect density increase significantly
Solution Approach 1:
The patent transitions from a conventional two-dimensional planar structure to a three-dimensional structure with connection layers and conduction layers arranged vertically on the semiconductor wafer unit. This dimensional change enables deeper current paths and improved voltage handling without requiring excessive increases in epitaxial layer thickness, thereby reducing cost and defect density while maintaining high voltage capability.
Solution Approach 2:
The patent employs a composite structure combining the semiconductor wafer unit with additional connection layers and conduction layers. This composite architecture integrates multiple functional layers that work together to achieve high voltage handling capability without relying solely on increased epitaxial layer thickness, thus avoiding the associated cost and defect penalties.
2Strength
If the wafer thickness is increased to enhance strength for single crystal epitaxial wafers, then the mechanical strength is improved, but the production cost and technical difficulty increase due to necessary backgrinding
Solution Approach 1:
The patent adopts a three-dimensional structure with vertically arranged connection layers and conduction layers on the semiconductor wafer unit. This vertical architecture provides mechanical reinforcement through layered construction without requiring increased overall wafer thickness, thereby eliminating the need for costly and technologically difficult backgrinding processes while maintaining structural strength.
3Manufacturing precision
If conventional semiconductor wafer materials are used to meet submicron CMOS production requirements, then the manufacturing precision is improved, but the compatibility with three-dimensional deep-PN-junction structure for high-voltage large-power devices is lost
Solution Approach 1:
The patent implements a three-dimensional structure with connection layers and conduction layers arranged vertically on the semiconductor wafer unit. This dimensional transformation enables the wafer to accommodate deep-PN-junction structures required for high-voltage large-power devices while maintaining compatibility with submicron CMOS production processes, thereby achieving both manufacturing precision and structural adaptability.
4Reliability
If the epitaxial layer thickness is increased to achieve higher working voltage, then the voltage handling capability is improved, but the power consumption bottleneck cannot be effectively reduced
Solution Approach 1:
The patent transitions to a three-dimensional structure with vertically arranged connection layers and conduction layers. This dimensional change creates more efficient current pathways and reduces resistive losses, enabling high working voltage capability while effectively reducing power consumption through improved electrical efficiency rather than relying on increased epitaxial layer thickness.
Data Source
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AI summary
A three-dimensional semiconductor wafer relates to a semiconductor wafer, including a semiconductor wafer unit (1), at least one connection layer, a conduction layer (3) and a protection layer (4), wherein the protection layer (4) is arranged on the conduction layer (3); and, the connection layer and the conduction layer (3) are arranged on the semiconductor wafer unit (1) at any surface of the semiconductor wafer unit (1). The present invention has a high practicability, an easy operation, a rigorous, coordinated and effective control plan, a smart design and an easy implementation, which saves energy, and meanwhile well meets requirements of customers and greatly improves a semiconductor performance.