3D IC Wafer Testing Apparatus with Single-Side Circuits
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Solution Overview
Problem
Current testing apparatuses for 3D IC chip stacking packaging structures are prone to damaging ultra-thin wafer substrates with TSVs due to contact pressure and cannot perform both chip probe (CP) and final tests (FT), complicating electrical circuit layouts and alignment.
Innovation Solution
A 3D IC wafer level testing apparatus with single-side electrical circuits on a base, featuring a recess with chamfers, an elastic part, and a vacuum system for precise positioning and contact, allowing for single-side testing and preventing damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pogo pins are used to contact the wafer substrate for testing, then electrical connection is achieved, but the ultra-thin wafer substrate is easily damaged due to contact pressure
Solution Approach 1:
The patent introduces an intermediary structure (the base with recess and elastic part) between the pogo pin and the wafer substrate. The elastic part acts as a mediator that distributes the contact pressure over a larger area, reducing the stress concentration that would damage the ultra-thin substrate while maintaining reliable electrical connection.
Solution Approach 2:
The recess structure is designed beforehand to accommodate the wafer substrate, and the elastic part provides pre-positioned cushioning. When the pogo pin contacts the substrate, the elastic part compresses to absorb excess force, preventing damage before it occurs. This beforehand cushioning mechanism protects the fragile substrate during the testing process.
2Reliability
If double-side electrical circuit loops are used for testing, then electrical connection is established, but the electrical circuit layout becomes complicated
Solution Approach 1:
The patent extracts the electrical circuit loops from the traditional double-side configuration and relocates them entirely to the base structure. By taking out the complexity from the wafer substrate side and placing all circuit loops on the base, the design simplifies the overall electrical circuit layout while maintaining testing functionality.
Solution Approach 2:
The patent transitions from a planar double-side circuit layout to a three-dimensional configuration where circuit loops extend vertically through the base and bend back to the surface. This dimensional change allows electrical connections to be established without requiring complex lateral routing on the wafer substrate side.
3Reliability
If contact pressure is applied for testing, then electrical connection is achieved, but accurate alignment in electrical circuit loops is compromised
Solution Approach 1:
The recess is designed beforehand to precisely accommodate the wafer substrate in the correct position. The elastic part provides cushioning that maintains constant contact pressure without requiring high force, thereby preventing alignment deviation that would occur with excessive pressure while ensuring reliable electrical connection.
Solution Approach 2:
The elastic part serves as an intermediary that decouples the alignment function from the contact pressure function. The recess structure handles alignment precision, while the elastic part provides gentle, distributed contact pressure, allowing both alignment accuracy and electrical connection reliability to be achieved simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate, damage-free testing of ultra-thin dies with both CP and FT capabilities, simplifying the testing process and ensuring precise alignment without deviation.
Implementation Method 1
a vacuum system for creating a vacuum environment
Implementation Method 2
an elastic part for preventing damage to the element to be tested
Data Source
AI summary
Disclosed is a testing apparatus, including: a base having opposite upper and lower surfaces, and a plurality of electrical circuits formed in the base, each of the electrical circuits extending from the upper surface to the lower surface and bending backwards to the upper surface such that two terminal ends of the electrical circuit are located on the upper surface. While in a testing, an element is disposed on the upper surface of the base such that testing probes are placed on the electrical contact spots of both the element and the upper surface of the base, thus without resorting to double sided testing that testing probes are placed on the upper and lower surfaces of the element as mentioned in the prior art. Hence, the testing apparatus and testing method can simplify the testing process and prevent the element from damage caused by mechanical stresses of the testing probes.