3D Semiconductor Layout With Wide Via for Smaller Logic Cells
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to improve electrical characteristics while scaling down MOS-FETs, which often leads to deterioration in operational properties due to increased design complexity and reduced design rules.
Innovation Solution
A three-dimensional semiconductor device is designed with a back-side metal layer, lower and upper channel patterns, source/drain patterns, and a wide via that electrically connects the upper and lower source/drain patterns, enhancing electrical connectivity and reducing area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to reduce pattern size and design rules, then device integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar two-dimensional transistor layouts to three-dimensional vertically stacked transistor structures. Multiple transistor channels are stacked vertically to achieve higher integration density without further reducing the lateral pattern size, thereby maintaining operational properties while improving area utilization.
Solution Approach 2:
The patent implements nested source/drain structures where upper source/drain patterns are positioned directly above lower source/drain patterns in a vertical stack. This nesting arrangement allows multiple transistor components to occupy the same lateral footprint while maintaining distinct functional layers, improving integration without compromising individual transistor performance.
2Area of moving object
If complex three-dimensional structures are implemented to improve integration density, then area requirements are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the source/drain structure into distinct upper and lower segments that can be formed through separate fabrication steps. This segmentation allows each portion to be optimized and manufactured independently using standard semiconductor processing techniques, reducing overall manufacturing complexity despite the three-dimensional architecture.
Solution Approach 2:
The patent forms preliminary source/drain patterns and channel structures in a bottom-up sequence, establishing the lower structures first before adding upper layers. This preliminary action approach enables better control over each fabrication step and simplifies the overall manufacturing process by avoiding complex top-down patterning requirements.
3Reliability
If wide vias are used to electrically connect upper and lower source/drain patterns, then electrical connectivity is improved, but area occupied by vias increases
Solution Approach 1:
The patent moves the electrical connection from a lateral two-dimensional via to a vertical three-dimensional connection through the stacked structure. The wide via connects upper source/drain patterns to lower source/drain patterns in the vertical dimension, achieving improved electrical connectivity while occupying minimal lateral area.
Data Source
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AI summary
A three-dimensional semiconductor device may include a back-side metal layer, a lower channel pattern on the back-side metal layer, first and second lower source/drain patterns, which are spaced apart from each other in a first direction with the lower channel pattern interposed therebetween, the first lower source/drain pattern being connected to the lower channel pattern, an upper channel pattern on the lower channel pattern, a first upper source/drain pattern on the first lower source/drain pattern, the first upper source/drain pattern being connected to the upper channel pattern, a second upper source/drain pattern on the second lower source/drain pattern, and a wide via electrically connecting the first upper source/drain pattern to the second lower source/drain pattern. The wide via may include first and second via portions having first and second top surfaces, and here, the second top surface may be located at a level lower than the first top surface.