3D Wiring Layout Around Bonding Pads in Semiconductor Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The layout of wirings in semiconductor devices is limited by the layout of bonding pads, restricting the degree of freedom and integration of the device.
Innovation Solution
The semiconductor device incorporates a wiring structure that is partially disposed over and under bonding pads, allowing for increased layout freedom and integration by using multiple bonding pad structures and wiring configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wirings are disposed only in spaces between bonding pads, then the wiring layout is constrained by bonding pad positions, but the device integration density is reduced
Solution Approach 1:
The patent applies dimensionality change by allowing wirings to be disposed not only in the horizontal plane between bonding pads but also vertically over and under the bonding pads. This three-dimensional wiring arrangement enables signals to route above and below bonding pad structures, effectively adding vertical dimension to the wiring layout and dramatically increasing both layout freedom and integration density.
2Adaptability or versatility
If multiple bonding pad structures are used, then the wiring layout flexibility is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the bonding pad functionality into multiple distinct bonding pad structures (first bonding pad structure, second bonding pad structure, third bonding pad structure) positioned at different locations and orientations. Each bonding pad structure can be independently configured and manufactured, allowing flexible wiring routing while maintaining manageable manufacturing complexity through modular design.
Data Source
AI summary
A semiconductor device may include a transistor on a substrate, a first wiring structure on the transistor, a first bonding pad structure on the first wiring structure, a second wiring structure on the first wiring structure and at least partially overlapping the first bonding pad structure in a horizontal direction, a second bonding pad structure on and spaced apart from the second wiring structure and overlapping the first bonding pad structure in the horizontal direction, a bit line structure on the first and second bonding pad structures, a gate structure on the bit line structure, a channel adjacent to the gate structure and in contact with the bit line structure, and a capacitor on the channel.