3D Word Line Pad Structure for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in increasing memory cell density and reducing parasitic capacitance in three-dimensional memory devices, which are essential for miniaturized memory devices with larger capacities.
Innovation Solution
The semiconductor device incorporates a word line stack with a plurality of word lines stacked perpendicular to a surface, featuring dielectric layers and bridge prevention layers to prevent short circuits, along with contact plugs coupled to word line pad portions, and a method for fabricating this structure involving the formation of a cell stack body, recesses, and filling with word lines and pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in three-dimensional arrangements to increase capacity, then memory cell density increases, but parasitic capacitance increases
Solution Approach 1:
The word line structure is segmented into multiple pad portions (first word line pad portion, second word line pad portion, etc.) stacked vertically. This segmentation allows each pad portion to be independently managed and connected through separate contact plugs, reducing the overall parasitic capacitance while maintaining high memory cell density in the three-dimensional structure.
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell arrangements to three-dimensional vertical stacking of word line pad portions and memory cells. By utilizing the vertical dimension, the device achieves higher memory cell density without proportionally increasing parasitic capacitance, as the contact plugs provide direct vertical pathways that minimize capacitive coupling.
2Productivity
If word line pad portions are stacked vertically to increase integration, then manufacturing complexity increases, but short circuits may occur between adjacent pads
Solution Approach 1:
Dielectric layers are introduced as intermediary materials between the stacked word line pad portions. These dielectric layers act as insulating barriers that prevent electrical short circuits between adjacent pads while allowing the vertical stacking structure to maintain its high integration level. The dielectric material mediates between the conductive pad portions, ensuring electrical isolation.
Solution Approach 2:
The patent applies different material properties to different regions: conductive materials for the word line pad portions and contact plugs, and insulating dielectric materials between them. This local differentiation of material quality ensures that each region performs its specific function - conduction where needed and isolation where required - thereby preventing short circuits while maintaining integration.
3Reliability
If contact plugs are used to connect word line pad portions, then word line resistance is optimized, but device complexity increases
Solution Approach 1:
The contact plugs serve multiple functions simultaneously: they provide electrical connection between stacked word line pad portions, optimize word line resistance by providing low-resistance pathways, and act as structural support elements in the three-dimensional architecture. This multi-functionality reduces the need for additional specialized components, thereby optimizing resistance without proportionally increasing complexity.
Data Source
AI summary
A semiconductor device includes: a plurality of word line pad portions that are stacked over a lower structure in a direction perpendicular to a surface of the lower structure; horizontal-level dielectric layers between the word line pad portions; and bridge prevention layers disposed between the word line pad portions and covering ends of the horizontal-level dielectric layers.