3D Word Line Via Layout for Lower Delay and Smaller Memory Area
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Solution Overview
Problem
The increasing capacity and miniaturization of three-dimensional semiconductor devices lead to signal delay and voltage drop due to stacking, which existing technologies have not effectively addressed.
Innovation Solution
A three-dimensional semiconductor device with via plugs arranged in a zigzag pattern and shared word lines between cell regions, allowing via plugs to vertically penetrate through a word line stack, reducing area occupation and enabling efficient signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If via plugs are arranged in a conventional linear pattern, then the manufacturing process is simple, but the occupied area is larger and signal transmission efficiency is reduced
Solution Approach 1:
The via plugs are arranged in a zigzag pattern rather than a conventional linear or grid pattern. This asymmetric arrangement reduces the occupied area in the row direction while maintaining proper spacing and electrical connections, directly addressing the area reduction goal without excessive complexity
Solution Approach 2:
The via plugs have varying diameters in the row direction, transitioning from smaller to larger diameters. This dimensional variation allows for optimized signal transmission and area utilization, as the diameter change accommodates different electrical requirements while fitting within a compact footprint
2Area of stationary object
If multiple word lines are used to control cells in different cell regions, then each cell region can be independently controlled, but the device area and control circuit complexity increase
Solution Approach 1:
Cells in both the first and second cell regions share the same word lines. The word line stack extends continuously across both cell regions and the via plug region, allowing a single set of word lines to control cells in both regions. This merging approach reduces the overall device area and simplifies the control circuitry while maintaining proper cell control functionality
Solution Approach 2:
The shared word lines serve multiple functions by controlling cells in both the first cell region and the second cell region simultaneously. This multi-functionality reduces the number of word line sets needed, thereby reducing device area and control circuit complexity
3Area of stationary object
If via plugs have uniform diameters, then the manufacturing process is simpler, but signal transmission efficiency and area utilization are suboptimal
Solution Approach 1:
The via plugs have different diameters at different positions in the row direction. Specifically, via plugs have progressively larger diameters from left to right (or vice versa), with each via plug having a diameter different from its neighbors. This local variation optimizes signal transmission for different via plugs while accommodating area constraints, achieving better area utilization and signal efficiency
Solution Approach 2:
The diameter parameter of the via plugs is varied systematically in the row direction. This parameter change allows for optimized electrical performance and area utilization, with larger diameter via plugs potentially handling higher current or providing better mechanical support in certain regions
Data Source
AI summary
A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.