3DIC Package Backside PDN Layout for Power and Thermal Control
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high power efficiency and thermal management in multiple stacking tiers of 3D integrated circuit (3DIC) packages, particularly due to the limitations of existing packaging techniques and power distribution networks.
Innovation Solution
The integration of a power rail or power distribution network (PDN) on the backside of at least one power rail chip located in the middle region of the 3DIC package, along with face-to-face and face-to-back bonding configurations, and a monotonically increasing bonding pitch from the topmost tier to the bottommost tier, enhances power efficiency and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple stacking tiers are used in 3DIC packages to increase integration density, then component density and functionality are improved, but power efficiency and thermal management deteriorate
Solution Approach 1:
The patent transitions from planar power distribution to three-dimensional power rail integration within the stacked package structure. Power rails are formed in vertical vias through multiple tiers, enabling power delivery in the vertical dimension rather than only lateral distribution. This dimensional change allows efficient power supply to multiple stacking tiers without increasing lateral footprint, resolving the contradiction between high integration density and power efficiency.
Solution Approach 2:
The patent implements nested power distribution structures where power rails are embedded within the stacked package tiers. Conductive interconnects and power rails are nested within vias and through-holes of the substrate, with multiple functional layers nested vertically. This nesting approach consolidates power distribution infrastructure within the existing package volume, improving power efficiency without compromising integration density.
2Productivity
If multiple stacking tiers are used in 3DIC packages to increase integration density, then component density and functionality are improved, but thermal dissipation deteriorates
Solution Approach 1:
The patent introduces thermal vias and conductive interconnect structures as intermediary elements between active device layers and heat sinks. These intermediary thermal pathways conduct heat away from densely packed components in multiple tiers, enabling effective thermal management despite high integration density. The conductive interconnects serve dual purposes as electrical connections and thermal conduction pathways.
Solution Approach 2:
The patent establishes vertical thermal conduction pathways through the stacked package structure using through-substrate vias and conductive interconnects. Heat is dissipated in the vertical dimension from upper tiers to lower heat sink structures, rather than relying solely on lateral heat spreading. This vertical thermal management approach enables effective heat removal from high-density multi-tier configurations.
3Ease of manufacture
If bonding pitch is increased to simplify manufacturing, then ease of manufacture is improved, but device complexity increases due to non-uniform bonding requirements
Solution Approach 1:
The patent implements location-specific bonding configurations where different bonding pitches and techniques are applied to different regions of the package. Fine-pitch bonding is used for high-density interconnect regions, while coarser bonding is used for power and ground connections. This localized approach to bonding quality allows optimization of each bonding region for its specific functional requirements, balancing manufacturability with device complexity.
Solution Approach 2:
The patent divides the bonding process into multiple discrete stages with different bonding parameters for different tiers. Each stacking tier can have customized bonding specifications, allowing segmentation of the overall bonding process into manageable steps. This segmentation enables complex multi-tier bonding configurations to be executed through a series of simpler, standardized bonding operations.
Data Source
AI summary
A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.