3DIC Hybrid Bonding Pad Exposure for Uniform Contact Resistance

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving efficient integration and testing of three-dimensional integrated circuits (3DICs) due to complexities in forming reliable interconnects and maintaining uniform contact resistance between stacked chips, which affects yield and cost.

Innovation Solution

A method for forming 3DIC structures involves creating conductive pads and dielectric caps with specific etching processes to expose portions of the pads, followed by circuit probing and hybrid bonding techniques to ensure electrical connectivity and uniform contact resistance between chips, enhancing the integration and testing processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hybrid bonding techniques are used to ensure electrical connectivity between stacked chips, then reliability of interconnects is improved, but device complexity increases

Engineering Contradiction:

Improvereliability of interconnectsVSAvoidcomplexity of bonding processes

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming conductive pads and dielectric caps with specific patterns before the bonding process. The etching processes create pre-configured contact areas that ensure uniform contact resistance during subsequent hybrid bonding, reducing the complexity of the bonding operation itself while maintaining high reliability.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements local quality by creating dielectric caps that expose specific portions of conductive pads through selective etching. This localized modification ensures uniform contact resistance at the bonding interface while leaving other areas of the structure unchanged, thereby improving reliability without requiring complex modifications to the entire device.

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If etching processes are used to expose portions of conductive pads, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:

Improveuniformity of contact resistanceVSAvoidcomplexity of fabrication processes

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the dielectric layer into regions with different etching characteristics. The dielectric cap is selectively etched to expose specific portions of the conductive pad, creating distinct contact areas that ensure uniform contact resistance. This segmented approach simplifies the overall fabrication process by using standard etching techniques applied to patterned dielectric layers.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10886245B2Semiconductor structure, 3DIC structure and method of fabricating the same

Publication Date: 2021.01.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Provided is a three-dimensional integrated circuit (3DIC) structure including a first die and a second die bonded together by a hybrid bonding structure. One of the first die and the second die has a pad and a cap layer disposed over the pad. The cap layer exposes a portion of a top surface of the pad, and the portion of the top surface of the pad has a probe mark. A bonding metal layer of the hybrid bonding structure penetrates the cap layer to electrically connect to the pad. A method of fabricating the first die or the second die of 3DIC structure is also provided.