3DIC I/O Buffer Layout With Central ESD Region for Electromigration
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Solution Overview
Problem
In 3D integrated circuit (3DIC) packages, the sequence of connecting die-to-die pads to an ESD circuit and then to the buffer circuit creates a horizontal current path, leading to current crowding and degraded electromigration conditions.
Innovation Solution
The integration of a buffer circuit with an ESD protection structure in die-to-die I/O circuits, dividing the driving strength into two sub-buffer regions positioned on opposite sides of the ESD protection region, splits and shortens the horizontal current path, reducing output capacitance loading and enhancing electromigration resilience.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the buffer circuit is connected to the ESD circuit in sequence (die-to-die pad to ESD circuit to buffer circuit), then the ESD protection function is achieved, but current crowding occurs and electromigration conditions are degraded
Solution Approach 1:
The buffer circuit is divided into two sub-buffer regions positioned on opposite sides of the ESD protection region. This segmentation creates multiple current paths instead of a single horizontal path, distributing the current flow and reducing current crowding effects while maintaining ESD protection functionality.
Solution Approach 2:
The invention transitions from a single horizontal current path to a multi-dimensional current distribution by placing sub-buffer regions on opposite sides of the ESD region and connecting them through vertical via structures. This dimensional change creates parallel current paths that reduce electromigration stress.
2Ease of operation
If the horizontal current path is used to connect die-to-die pads to buffer circuit through ESD circuit, then circuit functionality is achieved, but current path length is excessive causing degraded electromigration conditions
Solution Approach 1:
The long horizontal current path is segmented into multiple shorter paths by dividing the buffer circuit into sub-buffer regions on opposite sides of the ESD region. Each sub-buffer region has its own shorter current path to the ESD circuit, reducing the overall current path length by 50% to 75%.
3Device complexity
If the buffer circuit driving strength is concentrated in a single region, then the circuit design is simple, but output capacitance loading is high and electromigration resilience is reduced
Solution Approach 1:
The buffer circuit driving strength is divided into two sub-buffer regions positioned on opposite sides of the ESD protection region. This segmentation reduces output capacitance loading on any single node and improves electromigration resilience by distributing current flow, while the overall circuit design remains relatively simple.
Data Source
AI summary
A method includes forming first and second transistors over a substrate, the first and second transistors being parts of a buffer circuit in an input/output (I/O) circuit; forming a third transistor over the substrate and interposing between the first and second transistors from a cross-sectional view, the third transistor being a part of an electrostatic discharge (ESD) circuit in the I/O circuit; forming a first metal line horizontally extending from above the first transistor across the third transistor to above the second transistor, wherein the first metal line is electrically coupled to the first, second, and third transistors.