3DIC Clock Phase Calibration for Cross-Die Timing Closure
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Solution Overview
Problem
Achieving timing closure in three-dimensional integrated circuits (3DICs) is challenging due to variations in process, voltage, and temperature across different semiconductor dies, leading to potential logical errors and decreased device performance.
Innovation Solution
A self-aligning clock calibration system that tracks and recovers clocks between chip-to-chip boundaries, using a multiphase generator to adjust clock signals and mitigate phase shifts, allowing for separate timing closure within each chip, and includes periodic updates to compensate for voltage and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional clock networks are used in 3DICs without calibration, then device complexity is reduced, but timing precision deteriorates due to PVT variations causing timing closure failures
Solution Approach 1:
The patent implements preliminary clock calibration during manufacturing to pre-compensate for PVT variations. Calibration data is stored in non-volatile memory and applied during operation to maintain timing precision without adding real-time calibration complexity
Solution Approach 2:
The patent introduces calibration data as an intermediary element that mediates between the clock network and PVT variations. This calibration information compensates for timing errors without requiring direct real-time intervention in the clock distribution network
2Measurement precision
If design changes are made to achieve timing closure (insertion of intermediate latches, reduction of maximum frequency), then timing precision is improved, but device performance deteriorates
Solution Approach 1:
The patent changes the parameter being controlled from fixed clock frequency to adjustable clock phase/timing parameters. By calibrating timing parameters based on actual PVT conditions, the system achieves timing closure without reducing maximum frequency or adding pipeline stages
3Reliability
If clock calibration systems are implemented in 3DICs, then timing margins are improved, but device complexity increases
Solution Approach 1:
The calibration data is determined during manufacturing and stored in non-volatile memory, performing the complex calibration work beforehand. This eliminates the need for complex real-time calibration circuits while maintaining timing margins during operation
Solution Approach 2:
The system uses its own operational data to automatically adjust timing parameters through the stored calibration information, eliminating the need for external calibration equipment or complex control circuits
Data Source
AI summary
Clock calibration adjustments are provided. Some embodiments disclosed herein are related to a device. A device can include a first conductive element configured to receive a first signal at a first functional block. The device can include a second conductive element configured to convey the first signal to a second functional block of the device. The device can include a third conductive element to receive a second signal from the second functional block, the second signal varying from the first signal according to a phase-shift. The device can include a first circuit configured to determine the phase-shift between the first signal and the second signal. The device can include a second circuit configured to generate a third signal based on the phase-shift, the first signal, the second signal.