3DIC Dummy Pad Offset Layout for Via-Free Wafer Bonding
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Solution Overview
Problem
Current 3D integrated circuit (3DIC) packaging techniques require additional processing time and cost due to the need for conductive vias to prevent short circuits between dummy pads, which increases the physical size and complexity of the package.
Innovation Solution
The use of offset positioning for dummy pads on stacked wafers eliminates the need for conductive vias by preventing physical and electrical connections between dummy pads, allowing for direct bonding without conductive vias, thereby reducing processing time and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive vias are added to prevent short circuits between dummy pads, then reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies asymmetry by offsetting the positioning of dummy pads between stacked wafers. Instead of aligning dummy pads directly with each other (symmetric arrangement), the dummy pads on the second wafer are positioned at offset locations relative to the first wafer, preventing direct contact and eliminating the need for conductive vias to prevent short circuits.
Solution Approach 2:
The patent extracts and eliminates the unnecessary conductive vias from the packaging structure. By recognizing that dummy pads do not require electrical connection and that their direct contact creates harmful short circuits, the invention removes the need for additional conductive via structures, simplifying the overall device complexity.
2Reliability
If conductive vias are added to prevent short circuits between dummy pads, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The asymmetric offset positioning of dummy pads eliminates the need for additional conductive via fabrication steps, reducing manufacturing complexity and cost while maintaining reliability by preventing short circuits through geometric separation rather than electrical isolation structures.
3Device complexity
If offset positioning is used for dummy pads, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The offset positioning pattern for dummy pads is predetermined and designed into the wafer fabrication process before stacking. By establishing the offset arrangement in advance during wafer manufacturing, the precision requirement is shifted to a controlled fabrication parameter rather than a challenging assembly parameter, making the overall process more manageable.
4Productivity
If direct bonding is performed without conductive vias, then productivity is improved, but reliability may be compromised
Solution Approach 1:
The asymmetric offset positioning provides inherent short circuit prevention through geometric separation, enabling direct bonding without conductive vias. The physical separation of dummy pads by design eliminates the risk of short circuits while allowing simpler, faster bonding processes to be used.
Solution Approach 2:
The potential harmful effect of dummy pad contact (short circuits) is converted into a beneficial design feature by intentionally offsetting their positions. This transforms what would be a reliability problem into a solution that enables simpler, more productive bonding processes without compromising reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and cost of packaging by eliminating the need for conductive vias, enhancing the efficiency and miniaturization of 3DICs while preventing short circuits.
Implementation Method 1
Two semiconductor wafers may be bonded together through suitable bonding techniques. The commonly used bonding techniques include direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding and/or the like.
Data Source
AI summary
A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.