3DIC Package Structure With Hybrid Bonding and Gap-Fill Thinning
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and efficient packaging for three-dimensional integrated circuits (3DICs), particularly in forming reliable connections and reducing area usage while maintaining electrical integrity.
Innovation Solution
The method involves forming a 3DIC structure by bonding dies to a wafer using a hybrid bonding process, with a redistribution layer and conductive vias to connect dies electrically, and a gap fill structure to cover and thin the bonding dies, allowing for efficient electrical connections and reduced area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hybrid bonding process is used to bond dies to wafer, then electrical connectivity and integration density are improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming conductive vias in the first die, bonding the first die to the wafer, forming conductive vias in the second die, bonding the second die to the wafer. This segmentation allows each bonding operation to be optimized independently while maintaining overall electrical connectivity.
Solution Approach 2:
The patent transitions from planar 2D packaging to 3D vertical stacking by bonding multiple dies to the wafer in different layers. This dimensional change enables higher integration density and improved electrical connectivity through vertical interconnects while managing complexity through systematic process design.
2Reliability
If redistribution layer and conductive vias are used to connect dies, then electrical connectivity is improved, but device complexity increases
Solution Approach 1:
The conductive vias serve multiple functions: they provide electrical connection between dies, act as alignment features during bonding, and enable vertical signal routing. This multi-functionality reduces the need for separate structural elements, thereby managing complexity while improving connectivity.
Solution Approach 2:
The wafer acts as an intermediary substrate that receives and integrates multiple dies with their respective conductive vias. This intermediary structure simplifies the overall assembly by providing a common platform for electrical interconnection without requiring direct die-to-die bonding interfaces.
3Area of stationary object
If gap fill structure is used to cover and thin bonding dies, then area usage is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The gap fill structure systematically varies the thickness of the bonding die from the bonded interface toward the exposed surface. This controlled parameter change (thickness gradient) reduces the overall area requirement while managing precision requirements through progressive thinning rather than abrupt changes.
Solution Approach 2:
The gap fill structure is formed in advance to define the final thickness profile of the bonding die before subsequent processing steps. This preliminary action establishes the area reduction geometry early in the manufacturing sequence, allowing downstream processes to work with pre-defined thickness parameters.
Data Source
AI summary
A package structure includes a plurality of first dies, and a plurality of second dies. The plurality of first dies is on first regions of a semiconductor substrate. The plurality of second dies are electrically bonded to the plurality of first dies. The plurality of second dies covers second regions of the semiconductor substrate between the first regions of the semiconductor substrate. The first portion of top surfaces of the plurality of first dies are covered by the plurality of second dies, and the second portions of the top surfaces of the plurality of first dies are exposed by the plurality of second dies.