3DIC Hybrid Bonding Structure Without Metal Posts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3D integrated circuit (3DIC) technologies face challenges in increasing integration density and reducing turnaround time due to the complexity of forming high aspect ratio metal posts, which increases the risk of yield lowering and manufacturing time.
Innovation Solution
A 3D integrated circuit structure and manufacturing method that uses a substrate to electrically connect semiconductor dies instead of metal posts, incorporating a redistribution structure, molding material, and hybrid bonding to simplify the process and improve rigidity and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal posts are used to electrically connect semiconductor dies in 3D integrated circuits, then electrical connection between dies is achieved, but turnaround time increases and manufacturing complexity increases due to repeated exposure, development, etching, and deposition processes
Solution Approach 1:
The patent extracts and eliminates the metal post formation process from the 3D IC manufacturing flow. Instead of forming metal posts through repeated exposure, development, etching, and deposition, the invention directly bonds the upper semiconductor die to the lower semiconductor die through hybrid bonding, removing the intermediate metal post structure entirely and thereby reducing turnaround time while maintaining electrical connection reliability
Solution Approach 2:
The patent introduces hybrid bonding as an intermediary mechanism that directly connects the upper and lower semiconductor dies without requiring metal posts. The hybrid bonding process uses a combination of metallurgical bonding and mechanical interlocking to achieve reliable electrical connection, serving as a mediator that eliminates the need for complex metal post formation while ensuring robust electrical connectivity
2Reliability
If metal posts are used to electrically connect semiconductor dies in 3D integrated circuits, then electrical connection between dies is achieved, but manufacturing complexity increases due to repeated exposure, development, etching, and deposition processes
Solution Approach 1:
The patent extracts and eliminates the metal post formation process from the 3D IC manufacturing flow. Instead of forming metal posts through repeated exposure, development, etching, and deposition, the invention directly bonds the upper semiconductor die to the lower semiconductor die through hybrid bonding, removing the intermediate metal post structure entirely and thereby reducing manufacturing process complexity while maintaining electrical connection reliability
Solution Approach 2:
The patent introduces hybrid bonding as an intermediary mechanism that directly connects the upper and lower semiconductor dies without requiring metal posts. The hybrid bonding process uses a combination of metallurgical bonding and mechanical interlocking to achieve reliable electrical connection, serving as a mediator that eliminates the need for complex metal post formation while ensuring robust electrical connectivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces turnaround time, enhances product yield, and provides improved rigidity and resistance to warpage by eliminating the need for complex metal post formation, allowing for more efficient manufacturing of high-density 3D integrated circuits.
Implementation Method 1
performing hybrid bonding to electrically connect the lower surface of the second semiconductor die to an upper surface of the first semiconductor die and an upper surface of the substrate
Data Source
AI summary
Provided a three-dimensional (3D) integrated circuit structure including a redistribution structure, a first semiconductor die on the redistribution structure, a substrate on the redistribution structure and adjacent to the first semiconductor die, a molding material on the redistribution structure and between the first semiconductor die and the substrate, an interconnection structure on the substrate and the first semiconductor die, the interconnection structure including a plurality of first bonding pads and a plurality of second bonding pads, and each second bonding pad of the second bonding pads being directly bonded to each first bonding pad of the first bonding pads, and a second semiconductor die on the interconnection structure.