3DIC Wafer Interconnect Structure With Dielectric-Lined Conductive Plugs

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Solution Overview

Problem

The challenge in semiconductor manufacturing is to create smaller and more efficient packaging techniques for semiconductor devices, particularly in stacked semiconductor devices, to achieve higher integration density, reduced form factor, and lower power consumption.

Innovation Solution

The formation of interconnect structures between bonded semiconductor wafers using advanced bonding techniques and multi-layered dielectric films to protect against etching damage and ion diffusion, combined with conductive plugs to establish electrical connections across stacked wafers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If direct bonding or conventional bonding techniques are used to join semiconductor wafers, then the bonding process is simpler and faster, but etching damage and ion diffusion occur during subsequent processing

Engineering Contradiction:
Improvebonding process simplicityVSAvoidetching damage and ion diffusion
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

A dielectric layer is introduced as an intermediary between the semiconductor wafers to protect against etching damage and ion diffusion during subsequent processing steps, resolving the contradiction between bonding simplicity and protection against harmful effects

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric layer is applied beforehand to cushion and protect the semiconductor wafers from etching damage and ion diffusion that would otherwise occur during subsequent processing, preventing harmful effects before they can damage the devices

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Volume of moving object

If semiconductor wafers are stacked to reduce form factor, then integration density increases and power consumption decreases, but electrical connections between stacked wafers become more complex

Engineering Contradiction:
Improveform factorVSAvoidelectrical connection complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

Electrical connections are established through the thickness dimension of the stacked wafers using conductive plugs that penetrate through dielectric layers, transforming the connection problem from a planar to a vertical dimension and simplifying the overall interconnect architecture

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Conductive plugs are nested within dielectric layers to establish electrical connections between stacked wafers, with each plug embedded in its own dielectric environment, allowing complex interconnections to be built through systematic nesting of conductive and dielectric elements

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS12476224B23DIC interconnect apparatus and method
Publication Date: 2025.11.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12476224B2 patent drawing
  • US12476224B2 patent drawing
  • US12476224B2 patent drawing

AI summary

An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.