3D IC Interconnect via Single Conductive Plug
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and increasing integration density, with traditional packaging techniques failing to meet demands for smaller form factors, higher performance, and lower power consumption, particularly in stacked semiconductor devices where efficient interconnects are needed.
Innovation Solution
A method for forming interconnect structures in stacked semiconductor devices involves bonding two wafers using techniques like direct bonding, followed by a series of etching and deposition processes to create a single conductive plug that electrically couples active circuits across the wafers, reducing form factor and power consumption while preventing parasitic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple conductive plugs are used to connect stacked wafers, then electrical connection is achieved, but parasitic interference increases and device complexity increases
Solution Approach 1:
The patent merges multiple separate conductive plugs into a single shared conductive plug that serves multiple interconnect functions. This single plug connects multiple active circuits across stacked wafers, eliminating the parasitic interference associated with multiple separate plugs while maintaining reliable electrical connections.
Solution Approach 2:
The single conductive plug is designed to perform multiple functions simultaneously, serving as a shared interconnect for multiple active circuits. This multi-functional approach reduces the number of required plugs and their associated parasitic effects while achieving the necessary electrical connectivity.
2Ease of manufacture
If traditional packaging techniques are used, then manufacturing is simpler, but integration density is lower and form factor is larger
Solution Approach 1:
The patent transitions from traditional planar packaging to three-dimensional stacked wafer packaging. By stacking wafers vertically and using through-wafer conductive plugs, the design achieves higher integration density in the vertical dimension while maintaining manufacturing feasibility through established bonding and etching processes.
3Volume of moving object
If wafer stacking is implemented, then form factor is reduced, but interconnect complexity increases
Solution Approach 1:
The patent simplifies the interconnect structure in stacked wafers by merging multiple potential connection paths into a single shared conductive plug. This approach reduces interconnect complexity while achieving the necessary electrical connections between stacked wafers and maintaining compact form factor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher integration density and reduced form factor with lower power consumption by creating a single conductive plug for interconnects between stacked wafers, enhancing performance and reducing parasitic interference compared to multiple plug systems.
Implementation Method 1
Two semiconductor wafers may be bonded together through suitable bonding techniques. The commonly used bonding techniques include direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding and/or the like.
Implementation Method 2
A first opening may be formed in a first semiconductor chip of the stacked semiconductor device. A second opening may be formed that extends from a bottom of the first opening to a conductive feature in the second semiconductor chip
Implementation Method 3
The first opening and the second opening are filled with a conductive material
Data Source
AI summary
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.