3D IC Interconnect via Spacer-Shaped Dielectric Liners
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and integration density as traditional packaging techniques for semiconductor dies are limited in reducing physical size while maintaining performance and power efficiency, necessitating innovative methods for stacked semiconductor devices.
Innovation Solution
The method involves forming interconnect structures between stacked semiconductor wafers using various bonding techniques and multi-layered dielectric films to create conductive plugs that connect electrical circuits across wafers, allowing for efficient electrical connections and reduced form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional packaging techniques are used for semiconductor dies, then manufacturing simplicity is maintained, but integration density and performance are limited
Solution Approach 1:
The patent transitions from traditional 2D planar packaging to 3D stacked packaging, where multiple semiconductor wafers are vertically bonded together. This dimensional change enables significantly higher integration density by utilizing the vertical space above each die, allowing multiple functional layers to coexist in a compact footprint while maintaining manageable manufacturing processes through established bonding techniques.
Solution Approach 2:
The patent divides a single large-scale integrated circuit into multiple smaller semiconductor wafers, each containing a portion of the total circuit functionality. These segmented wafers are then stacked and interconnected through conductive plugs and vias, enabling higher overall integration density while keeping individual wafer fabrication processes simple and manageable using existing manufacturing capabilities.
2Volume of moving object
If stacked semiconductor wafers are used, then form factor is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary fabrication of conductive plugs, vias, and interconnect structures on each semiconductor wafer before the bonding process. This advance preparation ensures that all necessary electrical connections are pre-formed and positioned correctly, eliminating the need for complex post-bonding manufacturing steps and simplifying the overall fabrication process while achieving compact 3D stacking.
Solution Approach 2:
The patent introduces intermediate bonding layers and dielectric materials that facilitate the bonding process between stacked wafers. These intermediary materials enable reliable electrical and mechanical connections while providing a buffer that simplifies the bonding process, allowing standard manufacturing techniques to be used even as the number of stacked layers increases.
3Reliability
If conductive plugs and vias are formed through multi-layer dielectric films, then electrical connections are achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs a nested structure where conductive plugs are formed within vias that extend through multi-layer dielectric films, with each layer carefully aligned and positioned relative to the others. This nested arrangement, combined with preliminary formation of connection points on each wafer before stacking, ensures reliable electrical connections while managing alignment precision requirements through sequential, controlled fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher integration density and lower power consumption in semiconductor devices by facilitating effective electrical connections across stacked wafers, enhancing performance and reducing physical size.
Implementation Method 1
Two semiconductor wafers may be bonded together through suitable bonding techniques. The commonly used bonding techniques include direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermo-compressive bonding, reactive bonding and/or the like.
Data Source
AI summary
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.