3DIC Interconnect Structure for High-Density Wafer Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in further miniaturization and performance enhancement of semiconductor devices due to limitations in packaging techniques, particularly in achieving smaller form factors and lower power consumption while maintaining high integration density and performance.
Innovation Solution
The development of stacked semiconductor devices with interconnect structures formed between bonded wafers, utilizing various bonding techniques and advanced processing steps such as direct bonding, thinning, and multi-layered dielectric films to create electrical connections and passivation, enabling efficient integration of circuits and reduced form factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar packaging techniques are used, then manufacturing process is simple, but integration density is limited and form factor cannot be reduced further
Solution Approach 1:
The patent transitions from traditional planar (2D) packaging to three-dimensional stacked packaging, where multiple semiconductor wafers are bonded vertically to form a stack. This dimensional change enables significantly higher integration density by utilizing the vertical space, allowing more functional components to be packaged within a smaller footprint area while maintaining electrical connectivity through through-silicon vias and interconnect structures.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor wafers containing active circuits are stacked and bonded together, with each wafer containing nested functional blocks. The interconnect structures are nested within the substrate, with conductive plugs extending through multiple layers. This nesting approach maximizes the use of available space and achieves high integration density within a compact form factor.
2Volume of moving object
If multiple semiconductor wafers are stacked to reduce form factor, then device size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary processing steps on each semiconductor wafer before stacking, including forming through-silicon vias, depositing conductive plugs, and creating interconnect structures while the wafers are still separate and accessible. This preliminary action ensures that all necessary electrical connections and structural features are established before the wafers are bonded together, reducing the precision requirements during the bonding process itself and enabling better control over manufacturing tolerances.
3Productivity
If direct bonding of wafers is used, then process steps are reduced, but control over interconnect formation is limited
Solution Approach 1:
The patent segments the interconnect formation process into distinct stages: first forming conductive plugs in through-silicon vias, then forming separate conductive layers in interconnect regions, and finally bonding the wafers together. This segmentation allows each step to be optimized and controlled independently, ensuring precise formation of electrical connections while maintaining efficient production flow. The conductive plugs and interconnect structures are formed before bonding, allowing quality control at each stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased integration density, reduced form factors, and lower power consumption in semiconductor devices by effectively forming interconnect structures between stacked wafers, enhancing performance and enabling miniaturization beyond traditional limits.
Implementation Method 1
a first liner between a sidewall the conductive plug and the first substrate... The first liner may be referred to as a diffusion barrier layer, a diffusion prevention layer, or the like
Implementation Method 2
Two semiconductor wafers may be bonded together through suitable bonding techniques. The commonly used bonding techniques include direct bonding...
Data Source
AI summary
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.