3D Integrated Circuit Interconnects via Inter-Layer Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Two-dimensional integrated circuits face limitations in integration density due to physical constraints, and existing three-dimensional integrated circuits (3DIC) with through substrate vias (TSVs) face challenges in reducing total interconnect length effectively.
Innovation Solution
The implementation of a 3DIC structure with multiple tiers of cells connected via inter-layer vias (ILVs) that extend through substrates, allowing for reduced interconnect length and flexibility for engineering change orders (ECOs) without re-generating masks, utilizing low-k dielectric materials and conductive lines for efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If through substrate vias (TSVs) are used to connect stacked dies, then electrical connections between tiers are established, but total interconnect length is not sufficiently reduced
Solution Approach 1:
The patent transitions from conventional 2D interconnect routing to 3D interconnect architecture by stacking multiple dies vertically. Inter-layer vias (ILVs) provide vertical connections between tiers, fundamentally changing the interconnect topology from planar to spatial, thereby reducing overall signal path lengths and enabling higher integration density.
Solution Approach 2:
The patent divides the integrated circuit into multiple stacked tiers, each containing functional cells. This segmentation allows independent optimization of each tier and enables parallel processing paths. The inter-layer vias segment the vertical interconnect path into manageable sections, reducing the total interconnect length compared to a single-layer TSV architecture.
2Adaptability or versatility
If engineering change orders (ECOs) are implemented in conventional 3DIC, then design modifications are needed, but mask re-generation is required which increases cost and time
Solution Approach 1:
The patent implements reconfigurable inter-layer via connections that can be dynamically programmed after fabrication. The ILV structures include programmable switches or configurable routing elements that allow post-manufacturing design changes without requiring mask re-generation, enabling cost-effective ECOs while maintaining manufacturing simplicity.
Solution Approach 2:
The patent pre-provisions multiple ILV connection paths and redundant routing options during the initial design stage. This preliminary configuration of flexible interconnect structures allows future design changes to be implemented through software programming or simple reconfiguration rather than expensive physical mask changes, reducing future manufacturing costs.
3Quantity of substance
If minimum component size is reduced to improve 2D integration density, then more components can be integrated on the die, but aspect ratios and design rules become more constrained
Solution Approach 1:
The patent moves from 2D component placement to 3D stacking, where components (cells) are distributed across multiple vertical tiers. This dimensional transition eliminates the need to further reduce minimum component sizes for density improvement, as density is achieved through vertical stacking rather than horizontal compression, thereby relaxing aspect ratio and design rule constraints.
Data Source
AI summary
An apparatus includes a first tier and a second tier. The second tier is above the first tier. The first tier includes a first cell. The second tier includes a second cell and a third cell. The third cell includes a first inter layer via (ILV) to couple the first cell in the first tier to the second cell in the second tier. The third cell further includes a second ILV, the first ILV and the second ILV are extended along a first direction. The first tier further includes a fourth cell. The second tier further includes a fifth cell. The second ILV of the third cell is arranged to connect the fourth cell of the first tier with the fifth cell of the second tier. In some embodiments, the second tier further includes a spare cell including a spare ILV for engineering change order (ECO) purpose.