3DIC Lateral Interconnect Layer for Dense Vertical Connections
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Solution Overview
Problem
Current 3D multi-chip packaging methods face limitations in vertical and lateral signal and power connection density due to internal stress, alignment issues, and thermal expansion differences, leading to restricted bandwidth and performance degradation in 3DIC systems.
Innovation Solution
The use of ion cleaving technology to form cleave planes in semiconductor substrates, allowing for the creation of high-density interconnect networks that span across multiple device layers, enabling efficient vertical and lateral signal transmission through the implementation of an interconnect network layer with conductive structures and dielectric materials, and subsequent bonding and planarization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional TSV and interposer methods are used for vertical connections, then lateral signal connections can be provided, but vertical interconnect density is limited due to internal stress and alignment compensation requirements
Solution Approach 1:
The patent transitions from conventional 2.5D packaging with limited vertical TSV connections to true 3D stacking with high-density vertical interconnects. The interposer layer enables multiple dies to be stacked vertically with dense interconnect pathways in the vertical dimension, achieving high vertical interconnect density while maintaining alignment stability through the rigid interposer structure.
Solution Approach 2:
The interposer layer acts as an intermediary between stacked dies, providing a stable platform for vertical connections. It mediates the mechanical and thermal stresses between different die layers, allowing high-density TSV connections to be formed while maintaining alignment compensation. The interposer's rigid structure (silicon, glass, or plastic) provides a reference plane that stabilizes the vertical interconnect architecture.
2Area of stationary object
If thicker RDL interposers are used to provide lateral connections, then lateral signal transmission is improved, but vertical interconnect density is reduced due to via depth to thickness ratio constraints
Solution Approach 1:
The patent optimizes the interposer thickness parameter to achieve an optimal balance between lateral and vertical connections. By controlling the interposer thickness within specific ranges and adjusting the via depth-to-thickness ratio, the design enables both adequate lateral signal transmission and high vertical interconnect density. The interposer thickness is carefully selected to allow dense TSV formation while providing sufficient lateral connection pathways.
3Quantity of substance
If micron-diameter Cu vertical connection lines are used, then connection density is increased, but die-level stress increases due to CTE differences between Copper and Silicon
Solution Approach 1:
The interposer layer serves as a stress-mediating intermediary between the copper vertical interconnects and the silicon dies. It provides a transition layer that helps distribute and compensate for the thermal expansion stress generated by CTE mismatches. The interposer's material properties and structural design reduce the concentration of stress at critical interfaces, allowing high-density copper connections without excessive die-level stress.
Solution Approach 2:
The patent implements localized stress management around vertical interconnect regions. Kill zone regions are strategically placed around TSV locations to prevent active circuit elements from being positioned where stress concentration occurs. This local quality adjustment allows high-density vertical connections while protecting active circuits from stress-induced performance degradation through spatial separation.
4Reliability
If kill zone regions are inserted around vertical signal connection points, then device performance is protected from stress effects, but area available for active circuit elements is reduced
Solution Approach 1:
The patent applies local quality modification by creating kill zone regions with specific properties around vertical interconnect points. These regions have restricted circuit element placement to protect against stress effects, while the surrounding areas maintain full design flexibility. The kill zones are strategically positioned only where necessary around TSV locations, minimizing their impact on overall die area while providing localized stress protection for critical circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases inter-layer connection density and bandwidth, reducing thermal stress and mechanical constraints, thereby enhancing the performance and functionality of 3DIC systems by allowing for more efficient signal processing and communication between devices.
Implementation Method 1
implanting ions through the interconnect network layer to form a cleave plane in a semiconductor substrate
Implementation Method 2
an interconnect network layer with conductive structures and dielectric materials, and subsequent bonding and planarization processes
Data Source
AI summary
Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.