3DIC Top-Chip Local Interconnect for Body-Source Coupling
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Solution Overview
Problem
3DIC structures face challenges in maintaining sufficient area for body-source electrical coupling due to reduced space for electrical connections within and between devices, particularly in the top chip.
Innovation Solution
Incorporating a local interconnect within the insulator layer of the top chip to electrically connect the source and body regions, and forming a trench to expose these regions for connection, while maintaining the stacked structure with the bottom chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If chips are stacked vertically to form 3DIC structure, then two-dimensional area consumption is reduced, but available area for electrical connections within and between devices is reduced
Solution Approach 1:
The patent utilizes the vertical dimension within the chip structure by forming a trench that extends through the insulator layer to reach the body region. This allows the local interconnect to establish electrical coupling in the vertical direction rather than requiring lateral space, thereby resolving the contradiction between reduced chip package area and sufficient connection area.
Solution Approach 2:
The patent introduces a local interconnect as an intermediary element that mediates the electrical connection between the source region and body region. This local interconnect, positioned within the insulator layer and connected via a trench, serves as a mediator to achieve body-source coupling without requiring additional lateral space on the chip surface.
2Reliability
If available area for electrical connections is reduced in top chip, then body-source electrical coupling becomes difficult to achieve, but increasing chip package thickness is not desirable
Solution Approach 1:
The patent segments the electrical connection path into distinct components: the local interconnect within the insulator layer, the trench extending to the body region, and the metallurgical contact between them. This segmentation allows each component to be optimized independently, achieving reliable body-source coupling through the localized trench structure without increasing overall chip package thickness.
Solution Approach 2:
The patent embeds the trench structure within the existing insulator layer of the top chip, creating a nested configuration where the connection pathway is integrated into the chip's internal structure. This nesting approach allows the body-source coupling mechanism to be housed within the chip's existing volume without adding to the external dimensions.
Data Source
AI summary
Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions; a body region on a channel region between the source and drain regions; and a gate structure adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: a source region between drain regions; a body region on a channel region between the source region and each drain region; and gate structures adjacent to and between the channel regions and the dielectric material layers. The first chip also includes an insulator layer on the transistor opposite the dielectric material layers, a trench in the insulator layer extending to the source and body regions, and a local interconnect at the bottom of the trench.