3DIC Memory Chips With Computational Logic-In-Memory
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Solution Overview
Problem
Traditional computing systems face inefficiencies in memory bandwidth and access capabilities, particularly when handling large sets of sparse data, leading to poor locality of reference and increased energy consumption due to memory administration, which hampers performance and causes memory access bottlenecks.
Innovation Solution
The implementation of three-dimensional (3D) integrated circuit (3DIC) memory chips with computational logic-in-memory (LiM) that integrates application-specific computational logic directly within the memory, allowing data processing without accessing an external bus, using vertical interconnect access structures (VIAs) to communicate between memory layers and perform computations internally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional CPU-based processing systems are used, then data can be processed using generalized computational units, but memory bandwidth limitations and access bottlenecks occur leading to poor performance
Solution Approach 1:
The patent merges memory and computational logic into a unified structure where computational LiM layers are integrated within the memory stack. This combination allows data to be processed in-place within the memory hierarchy, eliminating the need for constant data movement between separate memory and processing units, thereby resolving the memory access bottleneck that limits traditional CPU-based systems
Solution Approach 2:
The patent transitions from a traditional two-dimensional memory architecture to a three-dimensional stacked memory architecture with multiple computational LiM layers positioned at different vertical levels. This dimensional change enables parallel data access from multiple layers simultaneously and allows computational operations to occur at various depths within the memory stack, significantly improving both memory bandwidth and processing throughput
2Use of energy by moving object
If data is moved between CPU and memory through external buses, then data transfer can occur, but energy consumption increases due to ancillary memory administration
Solution Approach 1:
The computational LiM layers perform data processing operations autonomously within the memory stack without requiring constant CPU intervention or external bus transactions. The memory system serves itself by executing computational tasks in-place, reducing the energy overhead associated with data movement and memory management while improving processing efficiency
3Productivity
If computational logic is integrated into memory layers, then accelerated data processing is achieved, but device complexity increases
Solution Approach 1:
The patent segments the memory system into multiple functional layers, with computational LiM layers integrated at specific positions within the memory stack. Each computational layer is designed as a modular unit that can be independently configured for specific algorithms, allowing complex processing capabilities to be achieved through standardized, repeatable building blocks rather than monolithic complex structures
Data Source
AI summary
This disclosure relates to a three-dimensional (3D) integrated circuit (3DIC) memory chip including computational logic-in-memory (LiM) for performing accelerated data processing. Related memory systems and methods are also disclosed. In one embodiment, the 3DIC memory chip includes at least one memory layer that provides a primary memory configured to store data. The 3DIC memory chip also includes a computational LiM layer. The computational LiM layer is a type of memory layer having application-specific computational logic integrated into local memory while externally appearing as regular memory. The computational LiM layer and the primary memory are interconnected through through-silica vias (TSVs). In this manner, the computational LiM layer may load data from the primary memory with the 3DIC memory chip without having to access an external bus coupling the 3DIC memory chip to a central processing unit (CPU) or other processors to computationally process the data and generate a computational result.