3DIC Metal Stack Layout for Bonding Pitch and PPA Bottlenecks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
3DIC manufacturing is more expensive than manufacturing two 2DICs individually, and there is limited improvement in power and/or performance despite a 50% reduction in footprint due to high manufacturing costs associated with wafer bonding and through substrate vias, as well as limited improvements in power and performance due to large last metal level pitches.
Innovation Solution
A 3DIC design method and system that optimizes metal stack configurations and bonding pitches for first and second chips, ensuring the bonding pitch is at least as large as the last metal level pitches, allowing concurrent design of BEOL components to improve power, performance, and area (PPA) by avoiding bottlenecks in current flow and routing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If two chips are stacked to form a 3DIC with bonding elements connecting the last metal levels, then the footprint area is reduced by 50%, but the manufacturing cost increases significantly
Solution Approach 1:
The patent transitions from two-dimensional planar stacking to three-dimensional vertical stacking by introducing through-substrate vias that penetrate the substrate thickness. This enables multiple chips to be stacked vertically with interconnects extending through the substrate, achieving compact footprint while managing complexity through vertical integration rather than horizontal expansion
Solution Approach 2:
The patent implements a nested structure where bonding elements and interconnects are embedded within the substrate thickness. Through-substrate vias are formed by depositing conductive material into holes drilled through the substrate, creating nested interconnect structures that route signals between stacked chips while occupying minimal lateral space
2Quantity of substance
If bonding pitch is reduced to increase interconnect density, then more interconnects can be formed, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the interconnect structure into multiple independent components: bonding elements formed on chip surfaces, through-substrate vias drilled and filled separately, and metal layers deposited in distinct stages. This segmentation allows each component to be optimized and manufactured independently, reducing the cumulative precision requirements compared to forming all interconnects in a single process
Solution Approach 2:
The patent performs preliminary actions by pre-forming bonding elements on chip surfaces before stacking, and pre-drilling and pre-filling through-substrate vias in the substrate before chip assembly. This preliminary preparation of interconnect structures enables subsequent chip stacking and bonding processes to proceed with relaxed precision requirements, as the critical interconnect pathways are already established
Data Source
AI summary
A three-dimensional integrated circuit (3DIC) design method and system includes metal stack and bonding pitch optimization to improve power, performance, and area (PPA). The resulting 3DIC includes a first chip and a second chip. A last metal level of the second chip can be bonded to the last metal level of the first chip by bonding elements. The bonding pitch of the bonding elements can be at least as large as the pitches of the first chip last metal level and the second chip last metal level. The metal stack configurations of each chip may be the same or different. With different metal stack configurations, the total numbers of metal levels on each chip, the thicknesses of the metal levels on each chip and/or the pitches of the last metal levels on each chip may be different.