3D Integrated Circuit Multi-Core CPU Vertical Interconnects
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Solution Overview
Problem
Current CPU designs face inefficiencies in performance and power efficiency due to communication overhead when moving threads between different processor cores, as they incur latency and energy overhead from migrating architectural state and caches, and passing data across the chip.
Innovation Solution
The implementation of multi-processor core three-dimensional (3D) integrated circuits (ICs) with conductive inter-tier vertical interconnects (ITVs) allows for closer integration of processor cores across multiple semiconducting layers, reducing communication distance and latency by enabling direct electrical coupling between IC tiers, facilitating workload offloading and resource sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processor cores are designed to communicate with each other to offload workloads and share resources, then CPU performance is improved, but communication overhead with latency and energy consumption increases
Solution Approach 1:
The patent transitions from traditional 2D planar integration to 3D stacked integration using multiple IC tiers connected by vertical interconnects. This dimensional change reduces the physical distance between processor cores from horizontal chip traversal to vertical short-hop connections, thereby reducing communication latency and energy consumption while maintaining high CPU performance
2Productivity
If threads are moved between different processor cores to optimize performance, then workload distribution is improved, but architectural state migration overhead increases
Solution Approach 1:
By organizing processor cores across multiple IC tiers with vertical interconnects, the patent enables faster thread migration between cores. The reduced physical distance and optimized interconnect architecture minimize the time required to migrate architectural state during thread movement, improving workload distribution efficiency
3Device complexity
If processor cores are integrated on a single chip, then device complexity is reduced, but communication distance and latency increase
Solution Approach 1:
The patent uses 3D stacked integration to reconcile the contradiction between integration and communication speed. Multiple IC tiers are vertically stacked with short vertical interconnects, maintaining relatively simple device structure while dramatically reducing communication distance and latency compared to 2D planar layouts
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances CPU performance by minimizing communication latency and energy overhead, allowing for more efficient switching between cores and improving energy efficiency through reduced interconnect distances and direct inter-tier communication.
Implementation Method 1
conductive inter-tier vertical interconnects (ITVs) allows for closer integration of processor cores across multiple semiconducting layers, reducing communication distance and latency by enabling direct electrical coupling between IC tiers
Data Source
AI summary
Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores (“cores”) to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC. Because 3DICs can overlap different IC tiers and/or align similar components in the same IC tier, the cores can be designed and located between or within different IC tiers in a 3DIC to reduce communication distance associated with processor core communication to share workload and/or resources, thus improving performance of the multi-processor CPU design.