3DIC Package Structure for Die and Antenna Integration

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Solution Overview

Problem

Existing semiconductor device packaging technologies face challenges in efficiently integrating semiconductor dies and antenna elements while ensuring stable electrical connections and reliable signal transmission, particularly in three-dimensional integrated circuit (3DIC) structures.

Innovation Solution

A manufacturing method involving a carrier with a debond layer, redistribution circuit structures, conductive pillars, and antenna elements, followed by encapsulation and planarization, allows for the integration of semiconductor dies and antennas within a package structure, enabling stable electrical connections and signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor dies and antenna elements are integrated at the wafer level, then manufacturing efficiency is improved, but ensuring stable electrical connections and reliable signal transmission becomes more difficult

Engineering Contradiction:

Improvemanufacturing efficiencyVSAvoidelectrical connection stability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent segments the packaging process into wafer-level integration and subsequent dicing stages. Redistribution circuit structures are formed on the wafer before dicing, allowing electrical connections to be established while the wafer is still intact (improving manufacturing efficiency), and then individual packages are separated (maintaining connection stability through the dicing process).

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by forming redistribution circuit structures, conductive pillars, and bonding pads on the wafer level before dicing. This preliminary integration of electrical connection structures ensures that stable electrical connections are already in place before the wafer is separated into individual packages, thereby maintaining reliability while improving manufacturing efficiency.

Inventive Principle:

Principle #10Preliminary action

2Device complexity

If wafer level packaging is used, then manufacturing complexity is reduced, but integrating multiple semiconductor devices and antennas with different functions becomes more challenging

Engineering Contradiction:

Improvemanufacturing complexityVSAvoidintegration capability

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements a universal wafer-level packaging platform that can accommodate multiple semiconductor devices and antenna elements with different functions. The redistribution circuit structures and conductive pillars serve multiple purposes: providing electrical connections for different device types, enabling signal transmission, and supporting various packaging configurations. This multi-functional approach allows diverse devices to be integrated using the same fundamental process steps.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent utilizes three-dimensional integration by stacking semiconductor devices, antenna elements, and redistribution circuit structures in multiple layers. Conductive pillars extend vertically to connect different levels, while redistribution circuits are routed in planar and vertical paths. This dimensional approach enables complex multi-device integration within a compact package while maintaining relatively simple wafer-level manufacturing processes.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Productivity

If dicing is performed after wafer level packaging, then individual packages are obtained, but electrical connections and signal transmission may be compromised

Engineering Contradiction:

Improvepackage separation efficiencyVSAvoidconnection integrity after dicing

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary formation of robust electrical connection structures (conductive pillars, bonding pads, redistribution circuits) before the dicing process. These structures are designed and created while the wafer is intact, ensuring proper alignment and connection integrity. The dicing process then simply separates the already-connected packages without compromising the pre-established electrical connections.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent designs the electrical connection structures with sufficient mechanical strength and alignment tolerance to withstand the dicing process. Conductive pillars and bonding pads are dimensioned and positioned to provide a margin of safety against misalignment or damage during cutting, thereby cushioning against potential connection failures that could occur during package separation.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12512424B2Package, package structure and method of manufacturing the same

Publication Date: 2025.12.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.