3DIC Package Underfill Layout for CTE Mismatch and Warpage
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving optimal integration density and reducing warpage in three-dimensional integrated circuits (3DICs) due to CTE mismatch between semiconductor packages and underlying substrates.
Innovation Solution
The implementation of a molded underfill layer with a higher CTE than the encapsulation layer, surrounding the first bumps and the semiconductor package, to reduce CTE mismatch and improve warpage profile in 3DIC structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chips are stacked vertically to form 3DICs to improve integration density, then integration density and bandwidth are improved, but CTE mismatch between stacked chips and substrate causes warpage issues
Solution Approach 1:
The patent introduces an underfill material as an intermediary substance between the stacked chips and the substrate. This underfill material has a CTE value that is higher than the encapsulation layer, serving as a mediator to compensate for the CTE mismatch between the rigid chip stack and the substrate, thereby reducing warpage while maintaining the benefits of high integration density
Solution Approach 2:
The patent changes the CTE parameter of the underfill material to be higher than that of the encapsulation layer. This parameter modification allows the underfill to expand more during thermal cycling, compensating for the contraction of the chip stack and substrate, thus reducing warpage and improving reliability without sacrificing integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the CTE mismatch between the semiconductor package and the substrate, leading to improved warpage profiles and enhanced reliability of 3DIC structures.
Implementation Method 1
The CTE of the molded underfill layer is different from a CTE of the encapsulation layer of the semiconductor package, and thus, the molded underfill layer may reduce a CTE mismatch between the semiconductor package and the substrate
Data Source
AI summary
Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.