3DIC Package Structure with Dual-Side Redistribution Layers
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and efficient packaging of electronic components due to the limitations of existing packaging technologies, which struggle with miniaturization and increased complexity in three-dimensional integrated circuits (3DICs) and package structures.
Innovation Solution
The method involves forming a semiconductor structure using a carrier with a release layer, mounting a die with conductive vias and interconnection structures, and creating redistribution layers on both sides of the die to facilitate electrical connections, allowing for the formation of a 3DIC package with enhanced connectivity and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional packaging technologies are used, then manufacturing processes are simple, but integration density is low and package size is large
Solution Approach 1:
The patent transitions from traditional two-dimensional planar packaging to three-dimensional vertical stacking architecture. Multiple dies are stacked vertically with redistribution layers connecting different stacking levels, enabling high integration density by utilizing the vertical dimension rather than expanding package footprint area.
Solution Approach 2:
The patent implements a nested structure where multiple dies are stacked vertically within a compact package footprint. Each die is positioned at different vertical levels, with redistribution layers nesting between stacking levels to provide electrical connections, achieving high integration density within a small volume.
2Area of stationary object
If package size is reduced for miniaturization, then area utilization improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment marks and reference structures on each die and redistribution layer before stacking. These preliminary alignment features enable precise positioning during the stacking process, ensuring accurate electrical connections between dies at different levels while maintaining compact package dimensions.
3Adaptability or versatility
If three-dimensional integrated circuits are implemented, then connectivity is enhanced, but device complexity increases
Solution Approach 1:
The patent divides the interconnection structure into multiple redistribution layers, with each layer providing electrical connections between specific dies at particular vertical levels. This segmentation of the interconnection function across multiple layers simplifies the overall complexity by organizing connections in a modular fashion rather than requiring a single complex interconnection structure.
Data Source
AI summary
Embodiments of the disclosure provide a package structure and method of forming the same. The package structure includes a first die, a first encapsulant, a first RDL structure, a die stack structure and a second encapsulant. The first encapsulant laterally encapsulates the first die. The first RDL structure is electrically connected to the first die, and disposed on a first side of the first die and the first encapsulant. The die stack structure is electrically connected to the first die and disposed on a second side of the first die opposite to the first side. The second encapsulant is located over the first encapsulant and laterally encapsulating the die stack structure. A sidewall of the first encapsulant is aligned with a sidewall of the second encapsulant.